Altera Cyclone II DSP Development Board User Manual
Page 93

Altera Corporation
Reference Manual
C–7
August 2006
Cyclone II DSP Development Board
DAC_B_D3
V20
B16
DIMM_DQ50
DAC_B_D4
V21
B17
DIMM_DQ57
DAC_B_D5
B24
B18
ADC_A_SEN
DAC_B_D6
T23
B19
ADC_B_D4
DAC_B_D7
P23
B2
VGA_B2
DAC_B_D8
Y24
B20
ADC_B_D5
DAC_B_D9
V24
B21
ADC_B_D7
DIG_LSB_A
K2
B22
ADC_A_D8
DIG_LSB_B
U25
B23
ADC_A_D11
DIG_LSB_C
AA3
B24
DAC_B_D5
DIG_LSB_D
V1
B25
EVM_A20
DIG_LSB_DP
P7
B26
GND
DIG_LSB_E
V7
B3
USER_LED1
DIG_LSB_F
U23
B4
DIMM_DQ69
DIG_LSB_G
AC2
B5
DIMM_DQ66
DIG_MSB_A
Y21
B6
DIMM_DQS8
DIG_MSB_B
T7
B7
ADC_A_D2
DIG_MSB_C
AB23
B8
DIMM_DQS4
DIG_MSB_D
Y5
B9
DIMM_DM5
DIG_MSB_DP
V3
C1
3.3V
DIG_MSB_E
E1
C10
DIMM_DQ45
DIG_MSB_F
U1
C11
ADC_A_D5
DIG_MSB_G
W21
C12
DIMM_DQS5
DIMM_A_R0
AE4
C13
ADC_B_DCLK
DIMM_A_R1
AC8
C14
GND
DIMM_A_R10
AE5
C15
DIMM_DQ55
DIMM_A_R11
AD4
C16
DIMM_DM7
DIMM_A_R12
Y12
C17
DIMM_DQS7
DIMM_A_R13
AF7
C18
GND
DIMM_A_R14
AC5
C19
ADC_B_D3
DIMM_A_R15
AF13
C2
PROTO_IO12
DIMM_A_R2
AD6
C20
1.8V
Table C–1. Cyclone II EP2C70F672-C6ES FPGA Pin-Outs (Part 7 of 22)
Note (1)
Alphabetical by Signal Name
Alphabetical by Pin Number
Schematic Signal Name
Pin Number
Pin Number
Schematic Signal Name
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)