Altera Cyclone II DSP Development Board - Manual (Page 108)

C–22 Reference Manual Altera Corporation
Cyclone II DSP Development Board August 2006
Introduction
VREF E10 Y3 FPGA_TO_DAC_CLK
VREF E8 Y4 DAC_A_D6
VREF F13 Y5 DIG_MSB_D
AC24 Y6 GND_PLL
AE24 Y7 1.2V
N21 Y8 GND_PLL
Note to Table C–1 :
(1) Blank cells indicate no connection.
Table C–1. Cyclone II EP2C70F672-C6ES FPGA Pin-Outs (Part 22 of 22) Note (1)
Alphabetical by Signal Name Alphabetical by Pin Number
Schematic Signal Name Pin Number Pin Number Schematic Signal Name