Figure d–3 – Altera Cyclone II DSP Development Board User Manual
Page 111
Altera Corporation
Reference Manual
D–3
August 2006
Cyclone II DSP Development Board
Figure D–3. The JTAG Cable Connected to the ASI Connector J13
3.
Run the Quartus II software
4.
Select Programmer (Tools menu).
5.
In the Mode box, select Active Serial Programming, click Add File.
6.
Browse to the directory:
<install-path>\CycloneII_DSP_Kit-v6.0.1\Examples\
FactoryDesign_ChA
.
f
Software and hardware installation and setup are described in the DSP
Development Kit, Cyclone II Edition Getting Started User Guide.
7.
Select sines.pof and click Open.
8.
Turn on Program/Configure and click Start to program the EPCS64.
When the Progress bar reaches 100%, programing is complete.
9.
Press SYS RESET (SW7) to reset the hardware and reconfigure the
Cyclone II DSP development board in SYS RESET mode. You should
see the POWER LED (D1) turn on, indicating power is present, the
LEDs D2 through D5 (USER_LED0 through USER_LED4,
J13
ASI Connector
JTAG Cable
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)