Altera Cyclone II DSP Development Board User Manual
Page 92

C–6
Reference Manual
Altera Corporation
Cyclone II DSP Development Board
August 2006
Introduction
AUDIO_CLK
AB3
AE9
DIMM_DQ19
AUDIO_CSN
AC25
AF10
DIMM_DQ22
AUDIO_DIN
J21
AF11
1.8V
AUDIO_DOUT
B13
AF12
GND
AUDIO_LRCIN
W4
AF13
DIMM_A_R15
AUDIO_LRCOUT
AB2
AF14
DIMM_SYNC_CLK
AUDIO_MODE
AA2
AF15
GND
AUDIO_SCLK
R4
AF16
1.8V
AUDIO_SDIN
AD2
AF17
DIMM_DQ3
CLKIN_BOT
N25
AF18
DIMM_DQ6
CLKIN_TOP
N2
AF19
DIMM_DQS0
DAC_A_D0
AB1
AF2
GND
DAC_A_D1
AA1
AF20
DIMM_SDA
DAC_A_D10
P3
AF21
DIMM_ODT_R0
DAC_A_D11
U7
AF22
DIMM_CSN_R0
DAC_A_D12
R5
AF23
DIMM_BA_R1
DAC_A_D13
P6
AF24
1.8V
DAC_A_D2
AE3
AF25
GND
DAC_A_D3
AD3
AF3
1.8V
DAC_A_D4
U3
AF4
USER_DIPSW4
DAC_A_D5
T2
AF5
DIMM_A_R4
DAC_A_D6
Y4
AF6
DIMM_DQ30
DAC_A_D7
AA5
AF7
DIMM_A_R13
DAC_A_D8
V5
AF8
GND
DAC_A_D9
V6
AF9
DIMM_DQ23
DAC_B_D0
M4
B1
GND
DAC_B_D1
M5
B10
DIMM_DQ40
DAC_B_D10
W25
B11
DIMM_DQ52
DAC_B_D11
W26
B12
ADC_A_D6
DAC_B_D12
V25
B13
AUDIO_DOUT
DAC_B_D13
T25
B14
DIMM_DQS6
DAC_B_D2
U20
B15
DIMM_DQ54
Table C–1. Cyclone II EP2C70F672-C6ES FPGA Pin-Outs (Part 6 of 22)
Note (1)
Alphabetical by Signal Name
Alphabetical by Pin Number
Schematic Signal Name
Pin Number
Pin Number
Schematic Signal Name
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)