Altera Cyclone II DSP Development Board User Manual
Page 62
2–54
Reference Manual
Altera Corporation
Cyclone II DSP Development Board
August 2006
General Connectors
shows the connections from the Mictor connector to the
EP2C70 FPGA and the JTAG connector.
Figure 2–18. Mictor Connector Signaling
shows the J12 pin-outs to the EP2C70. Unless otherwise
noted, labels indicate EP2C70 pin numbers.
Figure 2–19. Mictor Connector (J12) Pin-Outs
Notes to
:
(1)
Pins 5, 6, 11, 15, 17, and 19 are not connected to the EPC335 FPGA.
(2)
Pins 12 and 14 are at 3.3V.
(3)
Pins 39 through 43 are GND.
EP2C35F672
(U12)
40
4
Mictor Connector
J12
JTAG Connector
J9
38 J5
37 D1
40 GND
(3)
39 GND
(3)
42 GND
(3)
41 GND
(3)
43 GND
(3)
36 H6
35 F1
34 G6
33 G1
32 F6
31 J3
30 L6
29 H1
28 L7
27 J1
26 K7
25 J2
24 J8
23 K1
22 G5
21 NC
20 F4
19
(1)
18 G4
17
(1)
16 G3
15
(1)
14 3.3
V
(2
)
13 L2
12 3.3
V
(2
)
11
(1)
10 C2
9 M3
8 F2
7 M2
6
(1)
5
(1)
4 NC
3 NC
2 NC
1 NC
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)