Altera Cyclone II DSP Development Board User Manual
Page 95
Altera Corporation
Reference Manual
C–9
August 2006
Cyclone II DSP Development Board
DIMM_DQ10
AC14
D3
EP2C_CSON
DIMM_DQ11
AD12
D4
GND
DIMM_DQ12
Y13
D5
VREF
DIMM_DQ13
Y14
D6
DIMM_DM4
DIMM_DQ14
AA13
D7
DIMM_DQ67
DIMM_DQ15
AE12
D8
DIMM_DQ33
DIMM_DQ16
AC11
D9
DIMM_DQ35
DIMM_DQ17
AD10
E1
DIG_MSB_E
DIMM_DQ18
AE10
E10
VREF
DIMM_DQ19
AE9
E11
GND
DIMM_DQ2
AE17
E12
DIMM_DQ47
DIMM_DQ20
AB12
E13
1.8V
DIMM_DQ21
AD11
E14
1.8V
DIMM_DQ22
AF10
E15
DIMM_DQ60
DIMM_DQ23
AF9
E16
GND
DIMM_DQ24
AB10
E17
1.8V
DIMM_DQ25
AA10
E18
ADC_B_D10
DIMM_DQ26
AE6
E19
GND
DIMM_DQ27
AE7
E2
PROTO_IO28
DIMM_DQ28
Y11
E20
ADC_B_D11
DIMM_DQ29
AA11
E21
GND_PLL
DIMM_DQ3
AF17
E22
USER_LED3
DIMM_DQ30
AF6
E23
EVM_A8
DIMM_DQ31
AA9
E24
EVM_A6
DIMM_DQ32
F11
E25
EVM_A2
DIMM_DQ33
D8
E26
EVM_A4
DIMM_DQ34
C8
E3
EP2C_ASDO
DIMM_DQ35
D9
E4
GND_PLL
DIMM_DQ36
G10
E5
USER_LED0
DIMM_DQ37
F10
E6
1.8V
DIMM_DQ38
A7
E7
GND
DIMM_DQ39
C9
E8
VREF
Table C–1. Cyclone II EP2C70F672-C6ES FPGA Pin-Outs (Part 9 of 22)
Note (1)
Alphabetical by Signal Name
Alphabetical by Pin Number
Schematic Signal Name
Pin Number
Pin Number
Schematic Signal Name
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)