Altera Cyclone II DSP Development Board User Manual
Page 81
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Altera Corporation
Reference Manual
A–3
August 2006
Cyclone II DSP Development Board
DIMM_DQ45
B10
C10
Yes
DIMM_DQ46
D10
D12
Yes
DIMM_DQ47
C10
E12
Yes
DIMM_DQ48
B16
F14
Yes
DIMM_DQ49
B15
D14
Yes
DIMM_DQ50
C15
B16
Yes
DIMM_DQ51
G13
G14
Yes
DIMM_DQ52
G14
B11
Yes
DIMM_DQ53
F14
G13
Yes
DIMM_DQ54
D14
B15
Yes
DIMM_DQ55
B11
C15
Yes
DIMM_DQ56
A18
A18
No
DIMM_DQ57
G16
B17
Yes
DIMM_DQ58
F16
G16
Yes
DIMM_DQ59
F15
G15
Yes
DIMM_DQ60
G15
E15
Yes
DIMM_DQ61
B17
A17
Yes
DIMM_DQ62
A17
F15
Yes
DIMM_DQ63
E15
F16
Yes
DIMM_DQ64
C7
G9
Yes
DIMM_DQ65
D7
C4
Yes
DIMM_DQ66
F9
B5
Yes
DIMM_DQ67
G9
D7
Yes
DIMM_DQ68
C4
F9
Yes
DIMM_DQ69
B5
B4
Yes
DIMM_DQ70
A5
A5
No
DIMM_DQ71
B4
C7
Yes
DIMM_DQS0
AF19
AF19
No
DIMM_DQS1
AE15
AE15
No
DIMM_DQS2
AE13
AE13
No
DIMM_DQS3
AE8
AE8
No
DIMM_DQS4
B8
B8
No
Table A–1. Cyclone II EP2C70F672 DSP Development Board to DIMM Pin Changes (Part 3 of 4)
Signal Name
Original DDR2 Core Location
EP2C70F672 Board
Location
Different
(Yes/No)
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)