Altera Cyclone II DSP Development Board User Manual
Page 37

Altera Corporation
Reference Manual
2–29
August 2006
Cyclone II DSP Development Board
Cyclone II DSP Development Board Components
lists the DDR2 SRAM DIMM pin-outs for the EP2C70F672
FPGA.
Table 2–21. DDR2 SDRAM DIMM Pin-Outs (Part 1 of 8)
Cyclone II (U12)
Signal Name
DIMM (J8) Signal
Name
DIMM (J8) Pin
Number
Cyclone II (U12)
Pin Number
DIMM_A_R0
DIMM_A0
188
AE4
DIMM_A_R1
DIMM_A1
183
AC8
DIMM_A_R2
DIMM_A2
63
AD6
DIMM_A_R3
DIMM_A3
182
Y10
DIMM_A_R4
DIMM_A4
61
AF5
DIMM_A_R5
DIMM_A5
60
AD7
DIMM_A_R6
DIMM_A6
180
AC6
DIMM_A_R7
DIMM_A7
58
AB8
DIMM_A_R8
DIMM_A8
179
AD5
DIMM_A_R9
DIMM_A9
177
AE11
DIMM_A_R10
DIMM_A10
70
AE5
DIMM_A_R11
DIMM_A11
57
AD4
DIMM_A_R12
DIMM_A12
176
Y12
DIMM_A_R13
DIMM_A13
196
AF7
DIMM_A_R14
DIMM_A14
174
AC5
DIMM_A_R15
DIMM_A15
173
AF13
DIMM_BA_R0
DIMM_BA0
71
Y18
DIMM_BA_R1
DIMM_BA1
190
AF23
DIMM_BA_R2
DIMM_BA2
54
AB15
DIMM_CASN
DIMM_CASN
74
AC22
DIMM_CK_N0
DIMM_CK_N0
186
AD19
DIMM_CK_N1
DIMM_CK_N1
138
AD21
DIMM_CK_N2
DIMM_CK_N2
221
AA20
DIMM_CK_P0
DIMM_CK_P0
185
AC21
DIMM_CK_P1
DIMM_CK_P1
137
AB20
DIMM_CK_P2
DIMM_CK_P2
220
AD22
DIMM_CKE_R0
DIMM_CKE0
52
AE21
DIMM_CKE_R1
DIMM_CKE1
171
AC19
DIMM_CSN_R0
DIMM_CSN0
193
AF22
DIMM_CSN_R1
DIMM_CSN1
76
AB18
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)