Altera Cyclone II DSP Development Board - Manual (Page 50)

2–42 Reference Manual Altera Corporation
Cyclone II DSP Development Board August 2006
Memory Components
Memory Mapping to the TMS320C6416 Digital Signal Processor
The Spectrum Digital DSP Starter Kit (DSK) for the TMS320C6416,
Revision E, featuring the TMS320C6416 digital signal processor,
interfaces with the Cyclone II DSP development board. This interface is
primarily used to memory map the EP2C70 FPGA to the TMS320C6416
processor address space allowing the Cyclone II DSP development board
to be used as n FPGA co-processor.
The SSRAM memory is bussed with connectors U34 and U40 to interface
with the TMS320C6416 board. The TMS320C6416 board brings out the
TMS320C6416’s External Memory Interface Connector (EMIF) memory
bus to two corresponding headers that connect to U34 and U40. See
“Expansion TI-EVM Connectors (U34, U40)” on page 2–47 .
The TMS320C6416 processor memory maps to the Cyclone II DSP
development board’s SSRAM and EP2C70 FPGA with two chip select
signals on the TMS320C6416 processor:
■
EVM_CEn2 selects the SSRAM
■
EVM_CEn3 selects the EP2C70 FPGA
1 The SSRAM cannot be accessed by the EP2C70 FPGA while the
TMS320C6416 board is accessing the SSRAM via the TI-EVM
connector.
Because the SSRAM and EP2C70 FPGA device are bussed, there
is a single naming convention for the signals on the Cyclone II
DSP development board. These signals are named relative to the
TMS320C6416 board’s EMIF interface. For a mapping of these
signal names to signals used on the SSRAM, see
Appendix B,
SSRAM Pin-Out Table .