4 initialization/application information, 1 code example, 4 initialization/application information -9 – Freescale Semiconductor ColdFire MCF52210 User Manual
Page 369: 1 code example -9
DMA Timers (DTIM0–DTIM3)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
22-9
22.4
Initialization/Application Information
The general-purpose timer modules typically, but not necessarily, follow this program order:
•
The DTMRn and DTXMRn registers are configured for the desired function and behavior.
— Count and compare to a reference value stored in the DTRRn register
— Capture the timer value on an edge detected on DTINn
— Configure DTOUTn output mode
— Increment counter by 1 or by 65,537 (16-bit mode)
— Enable/disable interrupt or DMA request on counter reference match or capture edge
•
The DTMRn[CLK] register is configured to select the clock source to be routed to the prescaler.
— Internal bus clock (can be divided by 1 or 16)
— DTINn, the maximum value of DTINn is 1/5 of the internal bus clock, as described in the
device’s electrical characteristics
NOTE
DTINn may not be configured as a clock source when the timer capture
mode is selected or indeterminate operation results.
•
The 8-bit DTMRn[PS] prescaler value is set.
•
Using DTMRn[RST], counter is cleared and started.
•
Timer events are managed with an interrupt service routine, a DMA request, or by a software
polling mechanism.
22.4.1
Code Example
The following code provides an example of how to initialize and use DMA Timer0 for counting time-out
periods.
DTMR0 EQU IPSBARx+0x400 ;Timer0 mode register
DTMR1 EQU IPSBARx+0x440 ;Timer1 mode register
DTRR0 EQU IPSBARx+0x404 ;Timer0 reference register
DTRR1 EQU IPSBARx+0x444 ;Timer1 reference register
DTCR0 EQU IPSBARx+0x408 ;Timer0 capture register
DTCR1 EQU IPSBARx+0x448 ;Timer1 capture register
DTCN0 EQU IPSBARx+0x40C ;Timer0 counter register
DTCN1 EQU IPSBARx+0x44C ;Timer1 counter register
DTER0 EQU IPSBARx+0x403 ;Timer0 event register
DTER1 EQU IPSBARx+0x443 ;Timer1 event register
* TMR0 is defined as: *
*[PS] = 0xFF,
divide clock by 256
*[CE] = 00
disable capture event output
*[OM] = 0
output=active-low pulse
*[ORRI] = 0,
disable ref. match output
*[FRR] = 1,
restart mode enabled
*[CLK] = 10,
internal bus clock/16
*[RST] = 0,
timer0 disabled
move.w #0xFF0C,D0
move.w D0,TMR0