Freescale Semiconductor ColdFire MCF52210 - Manual (Page 201)

General Purpose I/O Module
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 13-7
13.6.3 Port Pin Data/Set Data Registers (PORTnP/SETn)
The PORTnP/SETn registers reflect the current pin states and control the setting of output pins when the
pin is configured for digital I/O.
The PORTnP/SETn registers with a full 8-bit implementation are shown in Figure 13-12 . The remaining
PORTnP/SETn registers use fewer than eight bits. Their bit definitions are shown in Figure 13-13 ,
Figure 13-14 , Figure 13-15 , and Figure 13-16 . The fields are described in Table 13-4 , which applies to all
PORTnP/SETn registers.
The PORTnP/SETn registers are read/write. At reset, the bits in the PORTnP/SETn registers are set to the
current pin states.
Reading a PORTnP/SETn register returns the current state of the port n pins.
Writing 1s to a PORTnP/SETn register sets the corresponding bits in the PORTn register. Writing 0s has
no effect.
IPSBAR
Offset: 0x10_0023 (DDRAS)
Access: User read/write
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0
DDRn1 DDRn0
W
Reset: 0 0 0 0 0 0 0 0
Figure 13-11. Port AS Data Direction Register (DDRAS)
Table 13-3. DDRn Field Descriptions
Field Description
DDRnx Sets data direction for port nx pin when the port is configured as a digital output.
1 DDRnx is configured as an output
0 DDRnx is configured as an input
IPSBAR
Offsets:
0x10_0044 (PORTDDP/SETDD)
0x10_003A (PORTANP/SETAN) Access: User read/write
7 6 5 4 3 2 1 0
R
PORTnP7 PORTnP6 PORTnP5 PORTnP4 PORTnP3 PORTnP2 PORTnP1 PORTnP0
W
Reset: 1 1 1 1 1 1 1 1
Figure 13-12. Port Pin Data/Set Data Registers with Bits 7:0 Implemented (PORTDD/SETDD,
PORTAN/SETAN)