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Ective interrupt enable bits (see, Section 15.4.1.10, “interrupt, Enable register (int_enb) – Freescale Semiconductor ColdFire MCF52210 User Manual

Page 246: 10 interrupt enable register (int_enb)

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Universal Serial Bus, OTG Capable Controller

MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2

15-18

Freescale Semiconductor

15.4.1.10 Interrupt Enable Register (INT_ENB)

The Interrupt Enable Register contains enable bits for each of the interrupt sources within the USB
Module. Setting any of these bits enables the respective interrupt source in the INT_STAT register. This
register contains the value of 0x00 after a reset.

Figure 15-16

shows the INT_ENB register.

IPSBAR

Offset:


0x1C_0084 (INT_ENB)

Access: User read/write

7

6

5

4

3

2

1

0

R

STALL_EN

ATTACH_EN

RESUME

_EN

SLEEP_EN

TOK_DNE

_EN

SOF_TOK

_EN

ERROR_E

N

USB_RST

_EN

W

Reset:

0

0

0

0

0

0

0

0

Figure 15-16. Interrupt Enable Register

Table 15-20. INT_ENB Field Descriptions

Field

Description

7

STALL_EN

STALL Interrupt Enable
0

The STALL interrupt is not enabled

1

The STALL interrupt is enabled

6

ATTACH_EN

ATTACH Interrupt Enable
0

The ATTACH interrupt is not enabled

1

The ATTACH interrupt is enabled

5

RESUME_EN

RESUME Interrupt Enable
0

The RESUME interrupt is not enabled

1

The RESUME interrupt is enabled

4

SLEEP_EN

SLEEP Interrupt Enable
0

The SLEEP interrupt is not enabled

1

The SLEEP interrupt is enabled

3

TOK_DNE

_EN

TOK_DNE Interrupt Enable
0

The TOK_DNE interrupt is not enabled

1

The TOK_DNE interrupt is enabled

2

SOF_TOK

_EN

SOF_TOK Interrupt Enable
0

The SOF_TOK interrupt is not enabled

1

The SOF_TOK interrupt is enabled

1

ERROR_EN

ERROR Interrupt Enable
0

The ERROR interrupt is not enabled

1

The ERROR interrupt is enabled

0

USB_RST

_EN

USB_RST Interrupt Enable
0

The USB_RST interrupt is not enabled

1

The USB_RST interrupt is enabled

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