Freescale Semiconductor ColdFire MCF52210 - Manual (Page 359)

General Purpose Timer Module (GPT)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 21-21
21.8 Reset
Reset initializes the GPT registers to a known startup state as described in Section 21.6, “Memory Map
and Registers .”
21.9 Interrupts
Table 21-24 lists the interrupt requests generated by the timer.
21.9.1 GPT Channel Interrupts (CnF)
A channel flag is set when an input capture or output compare event occurs. Clear a channel flag by writing
a 1 to it.
NOTE
When the fast flag clear all bit (GPTSCR1[TFFCA]) is set, an input capture
read or an output compare write clears the corresponding channel flag.
When a channel flag is set, it does not inhibit subsequent output compares
or input captures
21.9.2 Pulse Accumulator Overflow (PAOVF)
PAOVF is set when the 16-bit pulse accumulator rolls over from 0xFFFF to 0x0000. If the PAOVI bit in
GPTPACTL is also set, PAOVF generates an interrupt request. Clear PAOVF by writing a 1 to this flag.
NOTE
When the fast flag clear all enable bit (GPTSCR1[TFFCA]) is set, any
access to the pulse accumulator counter registers clears all the flags in
GPTPAFLG.
6
A successful output compare on channel 3 causes an output value determined by OC3Dn value to temporarily override the
output compare pin state of any other output compare channel.The next OC action for the specific channel continues to be
output to the pin. A channel 3 output compare can cause bits in the output compare 3 data register to transfer to the GPT port
data register, depending on the output compare 3 mask register.
Table 21-24. GPT Interrupt Requests
Interrupt Request Flag Enable Bit
Channel 3 IC/OC C3F C3I
Channel 2 IC/OC C2F C2I
Channel 1 IC/OC C1F C1I
Channel 0 IC/OC C0F C0I
PA overflow PAOVF PAOVI
PA input PAIF PAI
Timer overflow TOF TOI