Freescale Semiconductor ColdFire MCF52212 Instruction Manuals and User Guides
We have 1 Instruction Manual and User Guide for ColdFire MCF52212 Freescale Semiconductor
Manuals 
| Recognized languages: | English |
|---|---|
| Pages: | 576 |
| Size: | 6.54 MB |
Show table of contents
Document Outline
- Chapter 1 Overview
- 1.1 MCF52211 Family Configurations
- 1.2 Block Diagram
- 1.3 Part Numbers and Packaging
- 1.2 Features
- 1.2.1 V2 Core Overview
- 1.2.2 Integrated Debug Module
- 1.2.3 JTAG
- 1.2.4 On-Chip Memories
- 1.2.5 Power Management
- 1.2.6 USB On-The-Go Controller
- 1.2.7 UARTs
- 1.2.8 I2C Bus
- 1.2.9 QSPI
- 1.2.10 Fast ADC
- 1.2.11 DMA Timers (DTIM0-DTIM3)
- 1.2.12 General Purpose Timer (GPT)
- 1.2.13 Periodic Interrupt Timers (PIT0 and PIT1)
- 1.2.14 Real-Time Clock (RTC)
- 1.2.15 Pulse-Width Modulation (PWM) Timers
- 1.2.16 Software Watchdog Timer
- 1.2.17 Backup Watchdog Timer
- 1.2.18 Phase-Locked Loop (PLL)
- 1.2.19 Interrupt Controller (INTC)
- 1.2.20 DMA Controller
- 1.2.21 Reset
- 1.2.22 GPIO
- Chapter 2 Signal Descriptions
- 2.1 Introduction
- 2.2 Overview
- 2.3 Pin Functions
- 2.4 Reset Signals
- 2.5 PLL and Clock Signals
- 2.6 Mode Selection
- 2.7 External Interrupt Signals
- 2.8 Queued Serial Peripheral Interface (QSPI)
- 2.9 I2C I/O Signals
- 2.10 UART Module Signals
- 2.11 DMA Timer Signals
- 2.12 ADC Signals
- 2.13 General Purpose Timer Signals
- 2.14 Pulse-Width Modulator Signals
- 2.15 Debug Support Signals
- 2.16 EzPort Signal Descriptions
- 2.17 Power and Ground Pins
- Chapter 3 ColdFire Core
- Chapter 4 Multiply-Accumulate Unit (MAC)
- Chapter 5 Static RAM (SRAM)
- Chapter 6 Clock Module
- Chapter 7 Backup Watchdog Timer (BWT) Module
- Chapter 8 Power Management
- Chapter 9 Chip Configuration Module (CCM)
- Chapter 10 Reset Controller Module
- Chapter 11 Real-Time Clock
- Chapter 12 System Control Module (SCM)
- Chapter 13 General Purpose I/O Module
- Chapter 14 Interrupt Controller Module
- 14.1 68K/ColdFire Interrupt Architecture Overview
- 14.2 Memory Map
- 14.3 Register Descriptions
- 14.3.1 Interrupt Pending Registers (IPRHn, IPRLn)
- 14.3.2 Interrupt Mask Register (IMRHn, IMRLn)
- 14.3.3 Interrupt Force Registers (INTFRCHn, INTFRCLn)
- 14.3.4 Interrupt Request Level Register (IRLRn)
- 14.3.5 Interrupt Acknowledge Level and Priority Register (IACKLPRn)
- 14.3.6 Interrupt Control Registers (ICRnx)
- 14.3.7 Software and Level m IACK Registers (SWIACKn, LmIACKn)
- 14.3.8 Global Level m IACK Registers (GLmIACK)
- 14.4 Low-Power Wakeup Operation
- Chapter 15 Universal Serial Bus, OTG Capable Controller
- Chapter 16 Edge Port Module (EPORT)
- Chapter 17 DMA Controller Module
- Chapter 18 ColdFire Flash Module (CFM)
- Chapter 19 EzPort
- Chapter 20 Programmable Interrupt Timers (PIT0-PIT1)
- Chapter 21 General Purpose Timer Module (GPT)
- 21.1 Introduction
- 21.2 Features
- 21.3 Block Diagram
- 21.4 Low-Power Mode Operation
- 21.5 Signal Description
- 21.6 Memory Map and Registers
- 21.6.1 GPT Input Capture/Output Compare Select Register (GPTIOS)
- 21.6.2 GPT Compare Force Register (GPCFORC)
- 21.6.3 GPT Output Compare 3 Mask Register (GPTOC3M)
- 21.6.4 GPT Output Compare 3 Data Register (GPTOC3D)
- 21.6.5 GPT Counter Register (GPTCNT)
- 21.6.6 GPT System Control Register 1 (GPTSCR1)
- 21.6.7 GPT Toggle-On-Overflow Register (GPTTOV)
- 21.6.8 GPT Control Register 1 (GPTCTL1)
- 21.6.9 GPT Control Register 2 (GPTCTL2)
- 21.6.10 GPT Interrupt Enable Register (GPTIE)
- 21.6.11 GPT System Control Register 2 (GPTSCR2)
- 21.6.12 GPT Flag Register 1 (GPTFLG1)
- 21.6.13 GPT Flag Register 2 (GPTFLG2)
- 21.6.14 GPT Channel Registers (GPTCn)
- 21.6.15 Pulse Accumulator Control Register (GPTPACTL)
- 21.6.16 Pulse Accumulator Flag Register (GPTPAFLG)
- 21.6.17 Pulse Accumulator Counter Register (GPTPACNT)
- 21.6.18 GPT Port Data Register (GPTPORT)
- 21.6.19 GPT Port Data Direction Register (GPTDDR)
- 21.7 Functional Description
- 21.8 Reset
- 21.9 Interrupts
- Chapter 22 DMA Timers (DTIM0-DTIM3)
- Chapter 23 Queued Serial Peripheral Interface (QSPI)
- Chapter 24 UART Modules
- 24.1 Introduction
- 24.2 External Signal Description
- 24.3 Memory Map/Register Definition
- 24.3.1 UART Mode Registers 1 (UMR1n)
- 24.3.2 UART Mode Register 2 (UMR2n)
- 24.3.3 UART Status Registers (USRn)
- 24.3.4 UART Clock Select Registers (UCSRn)
- 24.3.5 UART Command Registers (UCRn)
- 24.3.6 UART Receive Buffers (URBn)
- 24.3.7 UART Transmit Buffers (UTBn)
- 24.3.8 UART Input Port Change Registers (UIPCRn)
- 24.3.9 UART Auxiliary Control Register (UACRn)
- 24.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn)
- 24.3.11 UART Baud Rate Generator Registers (UBG1n/UBG2n)
- 24.3.12 UART Input Port Register (UIPn)
- 24.3.13 UART Output Port Command Registers (UOP1n/UOP0n)
- 24.4 Functional Description
- 24.5 Initialization/Application Information
- Chapter 25 I2C Interface
- Chapter 26 Analog-to-Digital Converter (ADC)
- 26.1 Introduction
- 26.2 Features
- 26.3 Block Diagram
- 26.4 Memory Map and Register Definition
- 26.4.1 Control 1 Register (CTRL1)
- 26.4.2 Control 2 Register (CTRL2)
- 26.4.3 Zero Crossing Control Register (ADZCC)
- 26.4.4 Channel List 1 and 2 Registers (ADLST1 and ADLST2)
- 26.4.5 Sample Disable Register (ADSDIS)
- 26.4.6 Status Register (ADSTAT)
- 26.4.7 Limit Status Register (ADLSTAT)
- 26.4.8 Zero Crossing Status Register (ADZCSTAT)
- 26.4.9 Result Registers (ADRSLTn)
- 26.4.10 Low and High Limit Registers (ADLLMTn and ADHLMTn)
- 26.4.11 Offset Registers (ADOFSn)
- 26.4.12 Power Control Register (POWER)
- 26.4.13 Voltage Reference Register (CAL)
- 26.5 Functional Description
- 26.5.1 Input MUX Function
- 26.5.2 ADC Sample Conversion
- 26.5.3 ADC Data Processing
- 26.5.4 Sequential vs. Parallel Sampling
- 26.5.5 Scan Sequencing
- 26.5.6 Scan Configuration and Control
- 26.5.7 Interrupt Sources
- 26.5.8 Power Management
- 26.5.9 ADC Clock
- 26.5.10 Voltage Reference Pins VREFH and VREFL
- 26.5.11 Supply Pins VDDA and VSSA
- Chapter 27 Pulse-Width Modulation (PWM) Module
- 27.1 Introduction
- 27.2 Memory Map/Register Definition
- 27.2.1 PWM Enable Register (PWME)
- 27.2.2 PWM Polarity Register (PWMPOL)
- 27.2.3 PWM Clock Select Register (PWMCLK)
- 27.2.4 PWM Prescale Clock Select Register (PWMPRCLK)
- 27.2.5 PWM Center Align Enable Register (PWMCAE)
- 27.2.6 PWM Control Register (PWMCTL)
- 27.2.7 PWM Scale A Register (PWMSCLA)
- 27.2.8 PWM Scale B Register (PWMSCLB)
- 27.2.9 PWM Channel Counter Registers (PWMCNTn)
- 27.2.10 PWM Channel Period Registers (PWMPERn)
- 27.2.11 PWM Channel Duty Registers (PWMDTYn)
- 27.2.12 PWM Shutdown Register (PWMSDN)
- 27.3 Functional Description
- Chapter 28 Debug Module
- 28.1 Introduction
- 28.2 Signal Descriptions
- 28.3 Real-Time Trace Support
- 28.4 Memory Map/Register Definition
- 28.4.1 Shared Debug Resources
- 28.4.2 Configuration/Status Register (CSR)
- 28.4.3 BDM Address Attribute Register (BAAR)
- 28.4.4 Address Attribute Trigger Register (AATR)
- 28.4.5 Trigger Definition Register (TDR)
- 28.4.6 Program Counter Breakpoint/Mask Registers (PBR0-3, PBMR)
- 28.4.7 Address Breakpoint Registers (ABLR, ABHR)
- 28.4.8 Data Breakpoint and Mask Registers (DBR, DBMR)
- 28.5 Background Debug Mode (BDM)
- 28.6 Real-Time Debug Support
- 28.7 Processor Status, Debug Data Definition
- 28.8 Freescale-Recommended BDM Pinout
- Chapter 29 IEEE 1149.1 Test Access Port (JTAG)
- Appendix A Register Memory Map Quick Reference
- Appendix B Revision History