Epson S1C63000 - Manual (Page 99)

S1C63000 CORE CPU MANUAL EPSON 93
CHAPTER 4: INSTRUCTION SET
INC [ir],n4 Increment location [ir] in specified radix 2 cycles
Function: [ir]
←
N’s adjust ([ir] + 1)
Increments (+1) the content of the data memory addressed by the ir register (X or Y). The
operation result is adjusted with n4 as the radix.
Code: Mnemonic MSB LSB
INC [%X],n4 1 1 1 0 1 1 0 0 0 [10H-n4] 1D80H–1D8FH
INC [%Y],n4 1 1 1 0 1 1 0 1 0 [10H-n4] 1DA0H–1DAFH
Flags: E I C Z
↓
– ↕ ↕
Mode: Src: Immediate data
Dst: Register indirect
Extended addressing: Valid
Extended LDB %EXT,imm8
operation: INC [%X],n4 [00imm8]
←
N’s adjust ([00imm8] + 1) (00imm8 = 0000H + 00H to FFH)
LDB %EXT,imm8
INC [%Y],n4 [FFimm8]
←
N’s adjust ([FFimm8] + 1) (FFimm8 = FF00H + 00H to FFH)
Note: n4 should be specified with a value from 1 to 16.
INC [ir]+,n4 Increment location [ir] in specified radix and increment ir reg. 2 cycles
Function: [ir]
←
N’s adjust ([ir] + 1), ir
←
ir + 1
Increments (+1) the content of the data memory addressed by the ir register (X or Y). The
operation result is adjusted with n4 as the radix. Then increments the ir register (X or Y). The
increment result of the ir register does not affect the flags.
Code: Mnemonic MSB LSB
INC [%X]+,n4 1 1 1 0 1 1 0 0 1 [10H-n4] 1D90H–1D9FH
INC [%Y]+,n4 1 1 1 0 1 1 0 1 1 [10H-n4] 1DB0H–1DBFH
Flags: E I C Z
↓
– ↕ ↕
Mode: Src: Immediate data
Dst: Register indirect
Extended addressing: Invalid
Note: n4 should be specified with a value from 1 to 16.