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Epson, Chapter 3: cpu operation – Epson S1C63000 User Manual

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EPSON

S1C63000 CORE CPU MANUAL

CHAPTER 3: CPU OPERATION

3. Instructions that set the stack pointer

LDB %SP1,%BA

LDB %SP2,%BA

These two instructions are also accepted after fetching the next instruction. However, these
instructions must be executed as a pair. When one of them is fetched at first, all the interrupts
including NMI are masked (interrupts cannot be accepted). Then, when the other instruction is
fetched, that mask is released and interrupts can be accepted after the next instruction is fetched.

CLK

PK

PL

PC

FETCH

BS16

DBS1/0

WR

RD

RDIV

DA00–DA15

D0–D3

M00–M15

NMI

IACK

NACK

IF

0

1

2

3

4

5

DUMMY

(0100H)

ANY

pc-3

pc-1

0100H

ANY

2

1

2

ANY

pc

SP2-1

DUMMY

SP1-1

F reg.

ANY

pc

Interrupt processing by the hardware

Interrupt sampling

ANY

LD %A,[%X]

0

3

ANY

[00xxH]

pc-2

LDB %EXT,imm8

ANY

00xxH

DUMMY

Interrupt sampling

Executing the interrupt service routine

Fig. 3.5.2.1 NMI sequence
(normal acceptance)

Fig. 3.5.2.2 NMI sequence
(interrupt acceptance
after 1 instruction)

CLK

PK

PL

PC

FETCH

BS16

DBS1/0

WR

RD

RDIV

DA00–DA15

D0–D3

M00–M15

NMI

IACK

NACK

IF

0

1

2

3

4

5

ANY

ANY

DUMMY

(0100H)

ANY

pc-2

pc-1

0100H

ANY

ANY

2

1

2

ANY

pc

SP2-1

DUMMY

SP1-1

ANY

F reg.

ANY

pc

Interrupt processing by the hardware Executing the interrupt service routine

Interrupt sampling

4–6 cycle

DUMMY

In this chart, the dummy fetch
cycle starts after fetching the
"LD %A, [%X]" instruction
that follows the "LDB %EXT,
imm8" instruction.