Epson S1C63000 - Manual (Page 149)

S1C63000 CORE CPU MANUAL EPSON 143
CHAPTER 4: INSTRUCTION SET
XOR [%ir],imm4 Exclusive OR immediate data imm4 and location [ir reg.] 2 cycles
Function: [ir]
←
[ir]
∀
imm4
Performs an exclusive OR operation of the 4-bit immediate data imm4 and the content of the
data memory addressed by the ir register (X or Y), and stores the result in that address.
Code: Mnemonic MSB LSB
XOR [%X],imm4 1 1 0 1 1 1 0 0 0 i3 i2 i1 i0 1B80H–1B8FH
XOR [%Y],imm4 1 1 0 1 1 1 0 1 0 i3 i2 i1 i0 1BA0H–1BAFH
Flags: E I C Z
↓
– – ↕
Mode: Src: Immediate data
Dst: Register indirect
Extended addressing: Valid
Extended LDB %EXT,imm8
operation: XOR [%X],imm4 [00imm8]
←
[00imm8]
∀
imm4 (00imm8 = 0000H + 00H to FFH)
LDB %EXT,imm8
XOR [%Y],imm4 [FFimm8]
←
[FFimm8]
∀
imm4 (FFimm8 = FF00H + 00H to FFH)
XOR [%ir]+,imm4 Exclusive OR immediate data imm4 and location [ir reg.] and increment ir reg. 2 cycles
Function: [ir]
←
[ir]
∀
imm4, ir
←
ir + 1
Performs an exclusive OR operation of the 4-bit immediate data imm4 and the content of the
data memory addressed by the ir register (X or Y), and stores the result in that address. Then
increments the ir register (X or Y). The flags change due to the operation result of the data
memory and the increment result of the ir register does not affect the flags.
Code: Mnemonic MSB LSB
XOR [%X]+,imm4 1 1 0 1 1 1 0 0 1 i3 i2 i1 i0 1B90H–1B9FH
XOR [%Y]+,imm4 1 1 0 1 1 1 0 1 1 i3 i2 i1 i0 1BB0H–1BBFH
Flags: E I C Z
↓
– – ↕
Mode: Src: Immediate data
Dst: Register indirect
Extended addressing: Invalid