Epson S1C63000 - Manual (Page 54)

48 EPSON S1C63000 CORE CPU MANUAL
CHAPTER 4: INSTRUCTION SET
4.2.4 List in alphabetical order
ADC %A,%A
%A,%B
%A,imm4
%A,[%X]
%A,[%X]+
%A,[%Y]
%A,[%Y]+
%B,%A
%B,%A,n4
%B,%B
%B,imm4
%B,[%X]
%B,[%X],n4
%B,[%X]+
%B,[%X]+,n4
%B,[%Y]
%B,[%Y],n4
%B,[%Y]+
%B,[%Y]+,n4
[%X],%A
[%X],%B
[%X],%B,n4
[%X],imm4
[%X],0,n4
[%X]+,%A
[%X]+,%B
[%X]+,%B,n4
[%X]+,imm4
[%X]+,0,n4
[%Y],%A
[%Y],%B
[%Y],%B,n4
[%Y],imm4
[%Y],0,n4
[%Y]+,%A
[%Y]+,%B
[%Y]+,%B,n4
[%Y]+,imm4
[%Y]+,0,n4
ADD %A,%A
%A,%B
%A,imm4
%A,[%X]
%A,[%X]+
%A,[%Y]
%A,[%Y]+
%B,%A
%B,%B
%B,imm4
%B,[%X]
%B,[%X]+
%B,[%Y]
%B,[%Y]+
%X,%BA
%X,sign8
%Y,%BA
%Y,sign8
[%X],%A
[%X],%B
1 1 0 0 1 1 1 1 1 0 0 0 X
1 1 0 0 1 1 1 1 1 0 0 1 X
1 1 0 0 1 1 1 0 0 i3 i2 i1 i0
1 1 0 0 1 1 1 1 0 0 0 0 0
1 1 0 0 1 1 1 1 0 0 0 0 1
1 1 0 0 1 1 1 1 0 0 0 1 0
1 1 0 0 1 1 1 1 0 0 0 1 1
1 1 0 0 1 1 1 1 1 0 1 0 X
1 0 0 0 0 1 1 0 1 [ 10H-n4 ]
1 1 0 0 1 1 1 1 1 0 1 1 X
1 1 0 0 1 1 1 0 1 i3 i2 i1 i0
1 1 0 0 1 1 1 1 0 0 1 0 0
1 1 1 0 1 1 1 0 0 [ 10H-n4 ]
1 1 0 0 1 1 1 1 0 0 1 0 1
1 1 1 0 1 1 1 0 1 [ 10H-n4 ]
1 1 0 0 1 1 1 1 0 0 1 1 0
1 1 1 0 1 1 1 1 0 [ 10H-n4 ]
1 1 0 0 1 1 1 1 0 0 1 1 1
1 1 1 0 1 1 1 1 1 [ 10H-n4 ]
1 1 0 0 1 1 1 1 0 1 0 0 0
1 1 0 0 1 1 1 1 0 1 1 0 0
1 1 1 0 1 0 1 0 0 [ 10H-n4 ]
1 1 0 0 1 1 0 0 0 i3 i2 i1 i0
1 1 1 0 1 0 0 0 0 [ 10H-n4 ]
1 1 0 0 1 1 1 1 0 1 0 0 1
1 1 0 0 1 1 1 1 0 1 1 0 1
1 1 1 0 1 0 1 0 1 [ 10H-n4 ]
1 1 0 0 1 1 0 0 1 i3 i2 i1 i0
1 1 1 0 1 0 0 0 1 [ 10H-n4 ]
1 1 0 0 1 1 1 1 0 1 0 1 0
1 1 0 0 1 1 1 1 0 1 1 1 0
1 1 1 0 1 0 1 1 0 [ 10H-n4 ]
1 1 0 0 1 1 0 1 0 i3 i2 i1 i0
1 1 1 0 1 0 0 1 0 [ 10H-n4 ]
1 1 0 0 1 1 1 1 0 1 0 1 1
1 1 0 0 1 1 1 1 0 1 1 1 1
1 1 1 0 1 0 1 1 1 [ 10H-n4 ]
1 1 0 0 1 1 0 1 1 i3 i2 i1 i0
1 1 1 0 1 0 0 1 1 [ 10H-n4 ]
1 1 0 0 1 0 1 1 1 0 0 0 X
1 1 0 0 1 0 1 1 1 0 0 1 X
1 1 0 0 1 0 1 0 0 i3 i2 i1 i0
1 1 0 0 1 0 1 1 0 0 0 0 0
1 1 0 0 1 0 1 1 0 0 0 0 1
1 1 0 0 1 0 1 1 0 0 0 1 0
1 1 0 0 1 0 1 1 0 0 0 1 1
1 1 0 0 1 0 1 1 1 0 1 0 X
1 1 0 0 1 0 1 1 1 0 1 1 X
1 1 0 0 1 0 1 0 1 i3 i2 i1 i0
1 1 0 0 1 0 1 1 0 0 1 0 0
1 1 0 0 1 0 1 1 0 0 1 0 1
1 1 0 0 1 0 1 1 0 0 1 1 0
1 1 0 0 1 0 1 1 0 0 1 1 1
1 1 1 1 1 1 1 0 1 0 0 0 X
0 1 1 0 0 s7 s6 s5 s4 s3 s2 s1 s0
1 1 1 1 1 1 1 0 1 0 0 1 X
0 1 1 0 1 s7 s6 s5 s4 s3 s2 s1 s0
1 1 0 0 1 0 1 1 0 1 0 0 0
1 1 0 0 1 0 1 1 0 1 1 0 0
1
↓
–
Ч
1
↓
–
Ч
1
↓
–
Ч
1
↓
– ●
1
↓
–
Ч
1
↓
– ●
1
↓
–
Ч
1
↓
–
Ч
2
↓
–
Ч
1 ↓ – Ч
1
↓
–
Ч
1 ↓ – ●
2
↓
– ●
1 ↓ – Ч
2
↓
–
Ч
1 ↓ – ●
2
↓
– ●
1 ↓ – Ч
2
↓
–
Ч
2 ↓ – ●
2
↓
– ●
2 ↓ – ●
2
↓
– ●
2 ↓ – ●
2
↓
–
Ч
2
↓
–
Ч
2
↓
–
Ч
2
↓
–
Ч
2
↓
–
Ч
2
↓
– ●
2
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2
↓
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2
↓
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2
↓
– ●
2
↓
–
Ч
2
↓
–
Ч
2
↓
–
Ч
2
↓
–
Ч
2
↓
–
Ч
1
↓
–
Ч
1
↓
–
Ч
1
↓
–
Ч
1
↓
– ●
1
↓
–
Ч
1 ↓ – ●
1
↓
–
Ч
1 ↓ – Ч
1
↓
–
Ч
1 ↓ – Ч
1
↓
– ●
1 ↓ – Ч
1
↓
– ●
1 ↓ – Ч
1
↓
– –
Ч
1 ↓ – – ●
1
↓
– –
Ч
1 ↓ – – ●
2
↓
– ●
2 ↓ – ●
A
←
A+A+C
A
←
A+B+C
A
←
A+imm4+C
A
←
A+[X]+C
A
←
A+[X]+C, X
←
X+1
A
←
A+[Y]+C
A
←
A+[Y]+C, Y
←
Y+1
B
←
B+A+C
B
←
N's adjust (B+A+C)
B ← B+B+C
B
←
B+imm4+C
B ← B+[X]+C
B
←
N's adjust (B+[X]+C)
B ← B+[X]+C, X ← X+1
B
←
N's adjust (B+[X]+C), X
←
X+1
B ← B+[Y]+C
B
←
N's adjust (B+[Y]+C)
B ← B+[Y]+C, Y ← Y+1
B
←
N's adjust (B+[Y]+C), Y
←
Y+1
[X] ← [X]+A+C
[X]
←
[X]+B+C
[X] ← N's adjust ([X]+B+C)
[X]
←
[X]+imm4+C
[X] ← N's adjust ([X]+0+C)
[X]
←
[X]+A+C, X
←
X+1
[X]
←
[X]+B+C, X
←
X+1
[X]
←
N's adjust ([X]+B+C), X
←
X+1
[X]
←
[X]+imm4+C, X
←
X+1
[X]
←
N's adjust ([X]+0+C), X
←
X+1
[Y]
←
[Y]+A+C
[Y]
←
[Y]+B+C
[Y]
←
N's adjust ([Y]+B+C)
[Y]
←
[Y]+imm4+C
[Y]
←
N's adjust ([Y]+0+C)
[Y]
←
[Y]+A+C, Y
←
Y+1
[Y]
←
[Y]+B+C, Y
←
Y+1
[Y]
←
N's adjust ([Y]+B+C), Y
←
Y+1
[Y]
←
[Y]+imm4+C, Y
←
Y+1
[Y]
←
N's adjust ([Y]+0+C), Y
←
Y+1
A
←
A+A
A
←
A+B
A
←
A+imm4
A
←
A+[X]
A
←
A+[X], X
←
X+1
A ← A+[Y]
A
←
A+[Y], Y
←
Y+1
B ← B+A
B
←
B+B
B ← B+imm4
B
←
B+[X]
B ← B+[X], X ← X+1
B
←
B+[Y]
B ← B+[Y], Y ← Y+1
X
←
X+BA
X ← X+sign8 (sign8=-128~127)
Y
←
Y+BA
Y ← Y+sign8 (sign8=-128~127)
[X]
←
[X]+A
[X] ← [X]+B
Mnemonic
Machine code
Operation Cycle Page
Flag EXT.
mode 12 E I C Z 11 10 9 8 7 6 5 4 3 2 1 0
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61
61
61
62
62
62
62
61
65
61
61
62
65
62
66
62
65
62
66
63
63
66
64
67
63
63
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64
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63
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66
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69
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68
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72
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70
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