Epson S1C63000 - Manual (Page 73)

S1C63000 CORE CPU MANUAL EPSON 67
CHAPTER 4: INSTRUCTION SET
ADC [%ir]+,%B,n4 Add with carry B reg. to location [ir reg.] in specified radix and increment ir reg. 2 cycles
Function: [ir]
←
N's adjust ([ir] + B + C), ir
←
ir + 1
Adds the content of the B register and carry (C) to the data memory addressed by the ir
register (X or Y). The operation result is adjusted with n4 as the radix. Then increments the ir
register (X or Y). The flags change due to the operation result of the data memory and the
increment result of the ir register does not affect the flags. The C flag is set by a carry according
to the radix.
Code: Mnemonic MSB LSB
ADC [%X]+,%B,n4 1 1 1 0 1 0 1 0 1 [10H-n4] 1D50H–1D5FH
ADC [%Y]+,%B,n4 1 1 1 0 1 0 1 1 1 [10H-n4] 1D70H–1D7FH
Flags: E I C Z
↓
– ↕ ↕
Mode: Src: Register direct
Dst: Register indirect
Extended addressing: Invalid
Note: n4 should be specified with a value from 1 to 16.
ADC [%ir],0,n4 Add carry to location [ir reg.] in specified radix 2 cycles
Function: [ir]
←
N's adjust ([ir] + 0 + C)
Adds the carry (C) to the data memory addressed by the ir register (X or Y). The operation
result is adjusted with n4 as the radix. The C flag is set by a carry according to the radix. This
instruction is useful for a carry processing to the highest digit of n based counters.
Code: Mnemonic MSB LSB
ADC [%X],0,n4 1 1 1 0 1 0 0 0 0 [10H-n4] 1D00H–1D0FH
ADC [%Y],0,n4 1 1 1 0 1 0 0 1 0 [10H-n4] 1D20H–1D2FH
Flags: E I C Z
↓
– ↕ ↕
Mode: Src: Register direct
Dst: Register indirect
Extended addressing: Valid
Extended LDB %EXT,imm8
operation: ADC [%X],0,n4 [00imm8]
←
N’s adjust ([00imm8] + 0 + C)
(00imm8 = 0000H + 00H to FFH)
LDB %EXT,imm8
ADC [%Y],0,n4 [FFimm8]
←
N’s adjust ([FFimm8] + 0 + C)
(FFimm8 = FF00H + 00H to FFH)
Note: n4 should be specified with a value from 1 to 16.