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Adc [%ir]+,0,n4 add %r,%r – Epson S1C63000 User Manual

Page 74

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68

EPSON

S1C63000 CORE CPU MANUAL

CHAPTER 4: INSTRUCTION SET

ADC [%ir]+,0,n4

ADD %r,%r'

Add r' reg. to r reg.

1 cycle

Function:

r

r + r'

Adds the content of the r' register (A or B) to the r register (A or B).

Code:

Mnemonic

MSB

LSB

ADD %A,%A

1

1

0

0

1

0

1

1

1

0

0

0

X

1970H, (1971H)

ADD %A,%B

1

1

0

0

1

0

1

1

1

0

0

1

X

1972H, (1973H)

ADD %B,%A

1

1

0

0

1

0

1

1

1

0

1

0

X

1974H, (1975H)

ADD %B,%B

1

1

0

0

1

0

1

1

1

0

1

1

X

1976H, (1977H)

Flags:

E

I

C

Z

Mode:

Src: Register direct
Dst: Register direct
Extended addressing: Invalid

Add carry to location [ir reg.] in specified radix and increment ir reg. 2 cycles

Function:

[ir]

N's adjust ([ir] + 0 + C), ir

ir + 1

Adds the carry (C) to the data memory addressed by the ir register (X or Y). The operation
result is adjusted with n4 as the radix. Then increments the ir register (X or Y). The flags
change due to the operation result of the data memory and the increment result of the ir
register does not affect the flags. The C flag is set by a carry according to the radix. This
instruction is useful for a carry processing of n based counters.

Code:

Mnemonic

MSB

LSB

ADC [%X]+,0,n4

1

1

1

0

1

0

0

0

1

[10H-n4]

1D10H–1D1FH

ADC [%Y]+,0,n4

1

1

1

0

1

0

0

1

1

[10H-n4]

1D30H–1D3FH

Flags:

E

I

C

Z

Mode:

Src: Register direct
Dst: Register indirect
Extended addressing: Invalid

Note:

n4 should be specified with a value from 1 to 16.