Bit [%ir],%r, Bit [%ir]+,%r – Epson S1C63000 User Manual
Page 86
80
EPSON
S1C63000 CORE CPU MANUAL
CHAPTER 4: INSTRUCTION SET
BIT [%ir],%r
Test bit of location [ir reg.] with r reg.
1 cycle
Function:
[ir]
∧
r
Performs a logical AND of the content of the r register (A or B) and the content of the data
memory addressed by the ir register (X or Y) to check the bits of the memory. The Z flag is
changed due to the operation result, but the content of the memory is not changed.
Code:
Mnemonic
MSB
LSB
BIT [%X],%A
1
1
0
1
0
1
1
1
0
1
0
0
0
1AE8H
BIT [%X],%B
1
1
0
1
0
1
1
1
0
1
1
0
0
1AECH
BIT [%Y],%A
1
1
0
1
0
1
1
1
0
1
0
1
0
1AEAH
BIT [%Y],%B
1
1
0
1
0
1
1
1
0
1
1
1
0
1AEEH
Flags:
E
I
C
Z
↓
–
–
↕
Mode:
Src: Register direct
Dst: Register indirect
Extended addressing: Valid
Extended
LDB
%EXT,imm8
operation:
BIT
[%X],%r
[00imm8]
∧
r (00imm8 = 0000H + 00H to FFH)
LDB
%EXT,imm8
BIT
[%Y],%r
[FFimm8]
∧
r (FFimm8 = FF00H + 00H to FFH)
BIT [%ir]+,%r
Test bit of location [ir reg.] with r reg. and increment ir reg.
1 cycle
Function:
[ir]
∧
r, ir
←
ir + 1
Performs a logical AND of the content of the r register (A or B) and the content of the data
memory addressed by the ir register (X or Y) to check the bits of the memory. The Z flag is
changed due to the operation result, but the content of the memory is not changed. Then
increments the ir register (X or Y). The increment result of the ir register does not affect the
flags.
Code:
Mnemonic
MSB
LSB
BIT [%X]+,%A
1
1
0
1
0
1
1
1
0
1
0
0
1
1AE9H
BIT [%X]+,%B
1
1
0
1
0
1
1
1
0
1
1
0
1
1AEDH
BIT [%Y]+,%A
1
1
0
1
0
1
1
1
0
1
0
1
1
1AEBH
BIT [%Y]+,%B
1
1
0
1
0
1
1
1
0
1
1
1
1
1AEFH
Flags:
E
I
C
Z
↓
–
–
↕
Mode:
Src: Register direct
Dst: Register indirect
Extended addressing: Invalid