Epson S1C63000 - Manual (Page 7)

S1C63000 CORE CPU MANUAL EPSON 1
CHAPTER 1: OUTLINE
CHAPTER
1 O
UTLINE
The S1C63000 is the core CPU of the 4-bit single chip microcomputer S1C63 Family that utilizes
original EPSON architecture. It has a large and linear addressable space, maximum 64K words (13 bits/
word) program memory (code ROM area) and maximum 64K words (4 bits/word) data memory (RAM,
data ROM and I/O area), and high speed, abundant instruction sets. It operates in a wide range of supply
voltage and features low power consumption. Furthermore, modularization of programs can be done
easily because the program memory does not need bank and page management and relocatable program-
ming is possible.
In addition, it has adopted a unified architecture and a peripheral circuit interface in memory mapped I/O
method to flexibly meet future expansion of the S1C63 Family.
1.1 Features
The S1C63000 boasts the below features.
Program memory Maximum 64K
×
13 bits (linear address, non-page method)
Data memory Maximum 64K
×
4 bits
Basic instruction set 47 types with 5 types of basic addressing modes and 3 types of extended
addressing modes
Instruction cycle 1 cycle (2 clocks), 2 cycles (4 clocks) and 3 cycles (6 clocks)
Register configuration Data register 2
×
4 bits
Index register 2
×
16 bits
Address extension register 8 bits
Program counter
16 bits
Stack pointer 2
×
8 bits
Condition flag 4 bits
Queue register 16 bits
Interrupt function NMI (Non Maskable Interrupt) vector 1
Hardware interrupt vector Maximum 15 vectors
Software interrupt vector
Maximum 63 vectors
Standby function HALT/SLEEP
Peripheral circuit interface Memory mapped I/O method
Pipeline processing 2 stages (fetch and execution) pipeline processing
1.2 Instruction Set Features
(1) It adopts high efficiency machine cycles, high speed and abundant instruction set.
Almost all standard instructions operate in 1 cycle (2 clock).
(2) Both the program space and the data space are designed as a 64K-word linear space without page
concept and can be addressed with 1 instruction.
(3) The instruction system includes relocatable jump instructions and allows a relocatable programming.
Thus modular programming and software library development can be realized easily, and it increases
an efficiency for developing applications.
(4) Memory management can be done easily by 5 types of basic addressing modes, 3 types of extended
addressing modes with the address extension register and 16-bit operation function that is useful in
address calculations.
(5) 8-bit data processing is possible using the table look-up instruction and other instructions.
(6) Some instructions support a numbering system, thus binary to hexadecimal software counters can be
made easily.