Epson S1C63000 - Manual (Page 135)

S1C63000 CORE CPU MANUAL EPSON 129
CHAPTER 4: INSTRUCTION SET
SBC [%ir],%B,n4 Subtract with carry B reg. from location [ir reg.] in specified radix 2 cycles
Function: [ir]
←
N’s adjust ([ir] - B - C)
Subtracts the content of the B register and carry (C) from the data memory addressed by the ir
register (X or Y). The operation result is adjusted with n4 as the radix. The C flag is set accord-
ing to the radix.
Code: Mnemonic MSB LSB
SBC [%X],%B,n4 1 1 1 0 0 0 1 0 0 n3 n2 n1 n0 1C40H–1C4FH
SBC [%Y],%B,n4 1 1 1 0 0 0 1 1 0 n3 n2 n1 n0 1C60H–1C6FH
Flags: E I C Z
↓
– ↕ ↕
Mode: Src: Register direct
Dst: Register indirect
Extended addressing: Valid
Extended LDB %EXT,imm8
operation: SBC [%X],%B,n4 [00imm8]
←
N’s adjust ([00imm8] - B - C) (00imm8 = 0000H + 00H to FFH)
LDB %EXT,imm8
SBC [%Y],%B,n4 [FFimm8]
←
N’s adjust ([FFimm8] - B - C) (FFimm8 = FF00H + 00H to FFH)
Note: n4 should be specified with a value from 1 to 16. When 16 is specified for n4, the low-order 4
bits of the machine code (n3–n0) become 0000B.
SBC [%ir]+,%B,n4
Subtract with carry B reg. from location [ir reg.] in specified radix and increment ir reg. 2 cycles
Function: [ir]
←
N’s adjust ([ir] - B - C), ir
←
ir + 1
Subtracts the content of the B register and carry (C) from the data memory addressed by the ir
register (X or Y). The operation result is adjusted with n4 as the radix. Then increments the ir
register (X or Y). The flags change due to the operation result of the data memory and the
increment result of the ir register does not affect the flags. The C flag is set according to the
radix.
Code: Mnemonic MSB LSB
SBC [%X]+,%B,n4 1 1 1 0 0 0 1 0 1 n3 n2 n1 n0 1C50H–1C5FH
SBC [%Y]+,%B,n4 1 1 1 0 0 0 1 1 1 n3 n2 n1 n0 1C70H–1C7FH
Flags: E I C Z
↓
– ↕ ↕
Mode: Src: Register direct
Dst: Register indirect
Extended addressing: Invalid
Note: n4 should be specified with a value from 1 to 16. When 16 is specified for n4, the low-order 4
bits of the machine code (n3–n0) become 0000B.