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Sbc [%ir],0,n4, Sbc [%ir]+,0,n4 – Epson S1C63000 User Manual

Page 136

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EPSON

S1C63000 CORE CPU MANUAL

CHAPTER 4: INSTRUCTION SET

SBC [%ir],0,n4

Subtract carry from location [ir reg.] in specified radix

2 cycles

Function:

[ir]

N’s adjust ([ir] - 0 - C)

Subtracts the carry (C) from the data memory addressed by the ir register (X or Y). The opera-
tion result is adjusted with n4 as the radix. The C flag is set according to the radix. This instruc-
tion is useful for borrow processing of n based counters.

Code:

Mnemonic

MSB

LSB

SBC [%X],0,n4

1

1

1

0

0

0

0

0

0 n3 n2 n1 n0 1C00H–1C0FH

SBC [%Y],0,n4

1

1

1

0

0

0

0

1

0 n3 n2 n1 n0 1C20H–1C2FH

Flags:

E

I

C

Z

Mode:

Src: Register direct
Dst: Register indirect
Extended addressing: Valid

Extended

LDB %EXT,imm8

operation:

SBC [%X],0,n4

[00imm8]

N’s adjust ([00imm8] - 0 - C) (00imm8 = 0000H + 00H to FFH)

LDB %EXT,imm8
SBC [%Y],0,n4

[FFimm8]

N’s adjust ([FFimm8] - 0 - C) (FFimm8 = FF00H + 00H to FFH)

Note:

n4 should be specified with a value from 1 to 16. When 16 is specified for n4, the low-order 4
bits of the machine code (n3–n0) become 0000B.

SBC [%ir]+,0,n4

Subtract carry from location [ir reg.] in specified radix and increment ir reg. 2 cycles

Function:

[ir]

N’s adjust ([ir] - 0 - C), ir

ir + 1

Subtracts the carry (C) from the data memory addressed by the ir register (X or Y). The opera-
tion result is adjusted with n4 as the radix. Then increments the ir register (X or Y). The flags
change due to the operation result of the data memory and the increment result of the ir
register does not affect the flags. The C flag is set according to the radix. This instruction is
useful for borrow processing of n based counters.

Code:

Mnemonic

MSB

LSB

SBC [%X]+,0,n4

1

1

1

0

0

0

0

0

1 n3 n2 n1 n0 1C10H–1C1FH

SBC [%Y]+,0,n4

1

1

1

0

0

0

0

1

1 n3 n2 n1 n0 1C30H–1C3FH

Flags:

E

I

C

Z

Mode:

Src: Register direct
Dst: Register indirect
Extended addressing: Invalid

Note:

n4 should be specified with a value from 1 to 16. When 16 is specified for n4, the low-order 4
bits of the machine code (n3–n0) become 0000B.