Epson S1C63000 - Manual (Page 111)

S1C63000 CORE CPU MANUAL EPSON 105
CHAPTER 4: INSTRUCTION SET
LD [%ir]+,[%ir’]+ Load location [ir’ reg.] into location [ir reg.] and increment ir and ir’ reg. 2 cycles
Function: [ir]
←
[ir’], ir
←
ir + 1, ir’
←
ir’ + 1
Loads the content of the data memory addressed by the ir’ register (X or Y) into the data
memory addressed by the ir register (Y or X). Then increments both the ir and ir’ registers.
Code: Mnemonic MSB LSB
LD [%X]+,[%Y]+ 1 1 1 1 0 1 1 1 1 1 1 1 1 1EFFH
LD [%Y]+,[%X]+ 1 1 1 1 0 1 1 1 1 1 1 0 1 1EFDH
Flags: E I C Z
↓
– – –
Mode: Src: Register indirect
Dst: Register indirect
Extended addressing: Invalid
LDB %BA,imm8 Load immediate data imm8 into BA reg. 1 cycle
Function: BA
←
imm8
Loads the 8-bit immediate data imm8 into the BA register.
Code: Mnemonic MSB LSB
LDB %BA,imm8 0 1 0 0 1 i7 i6 i5 i4 i3 i2 i1 i0 0900H–09FFH
Flags: E I C Z
↓
– – –
Mode: Src: Immediate data
Dst: Register direct
Extended addressing: Invalid