Epson S1C63000 - Manual (Page 58)

52 EPSON S1C63000 CORE CPU MANUAL
CHAPTER 4: INSTRUCTION SET
LDB %BA,%YH
%BA,%YL
%BA,imm8
%BA,[%X]+
%BA,[%Y]+
%EXT,%BA
%EXT,imm8
%SP1,%BA
%SP2,%BA
%XH,%BA
%XL,%BA
%XL,imm8
%YH,%BA
%YL,%BA
%YL,imm8
[%X]+,%BA
[%X]+,imm8
[%Y]+,%BA
NOP
OR %A,%A
%A,%B
%A,imm4
%A,[%X]
%A,[%X]+
%A,[%Y]
%A,[%Y]+
%B,%A
%B,%B
%B,imm4
%B,[%X]
%B,[%X]+
%B,[%Y]
%B,[%Y]+
%F,imm4
[%X],%A
[%X],%B
[%X],imm4
[%X]+,%A
[%X]+,%B
[%X]+,imm4
[%Y],%A
[%Y],%B
[%Y],imm4
[%Y]+,%A
[%Y]+,%B
[%Y]+,imm4
POP %A
%B
%F
%X
%Y
PUSH %A
%B
%F
%X
%Y
RET
RETD imm8
1 1 1 1 1 1 1 0 0 1 0 1 1
1 1 1 1 1 1 1 0 0 1 0 1 0
0 1 0 0 1 i7 i6 i5 i4 i3 i2 i1 i0
1 1 1 1 1 1 1 0 1 1 0 0 0
1 1 1 1 1 1 1 0 1 1 0 1 0
1 1 1 1 1 1 1 0 1 0 1 0 X
0 1 0 0 0 i7 i6 i5 i4 i3 i2 i1 i0
1 1 1 1 1 1 1 0 0 0 1 0 X
1 1 1 1 1 1 1 0 0 0 1 1 X
1 1 1 1 1 1 1 0 0 0 0 0 1
1 1 1 1 1 1 1 0 0 0 0 0 0
0 1 0 1 0 i7 i6 i5 i4 i3 i2 i1 i0
1 1 1 1 1 1 1 0 0 0 0 1 1
1 1 1 1 1 1 1 0 0 0 0 1 0
0 1 0 1 1 i7 i6 i5 i4 i3 i2 i1 i0
1 1 1 1 1 1 1 0 1 1 0 0 1
0 0 0 0 1 i7 i6 i5 i4 i3 i2 i1 i0
1 1 1 1 1 1 1 0 1 1 0 1 1
1 1 1 1 1 1 1 1 1 1 1 1 X
1 1 0 1 1 0 1 1 1 0 0 0 X
1 1 0 1 1 0 1 1 1 0 0 1 X
1 1 0 1 1 0 1 0 0 i3 i2 i1 i0
1 1 0 1 1 0 1 1 0 0 0 0 0
1 1 0 1 1 0 1 1 0 0 0 0 1
1 1 0 1 1 0 1 1 0 0 0 1 0
1 1 0 1 1 0 1 1 0 0 0 1 1
1 1 0 1 1 0 1 1 1 0 1 0 X
1 1 0 1 1 0 1 1 1 0 1 1 X
1 1 0 1 1 0 1 0 1 i3 i2 i1 i0
1 1 0 1 1 0 1 1 0 0 1 0 0
1 1 0 1 1 0 1 1 0 0 1 0 1
1 1 0 1 1 0 1 1 0 0 1 1 0
1 1 0 1 1 0 1 1 0 0 1 1 1
1 0 0 0 0 1 0 0 1 i3 i2 i1 i0
1 1 0 1 1 0 1 1 0 1 0 0 0
1 1 0 1 1 0 1 1 0 1 1 0 0
1 1 0 1 1 0 0 0 0 i3 i2 i1 i0
1 1 0 1 1 0 1 1 0 1 0 0 1
1 1 0 1 1 0 1 1 0 1 1 0 1
1 1 0 1 1 0 0 0 1 i3 i2 i1 i0
1 1 0 1 1 0 1 1 0 1 0 1 0
1 1 0 1 1 0 1 1 0 1 1 1 0
1 1 0 1 1 0 0 1 0 i3 i2 i1 i0
1 1 0 1 1 0 1 1 0 1 0 1 1
1 1 0 1 1 0 1 1 0 1 1 1 1
1 1 0 1 1 0 0 1 1 i3 i2 i1 i0
1 1 1 1 1 1 1 1 0 1 1 1 1
1 1 1 1 1 1 1 1 0 1 1 1 0
1 1 1 1 1 1 1 1 0 1 1 0 1
1 1 1 1 1 1 1 1 0 1 0 0 1
1 1 1 1 1 1 1 1 0 1 0 1 X
1 1 1 1 1 1 1 1 0 0 1 1 1
1 1 1 1 1 1 1 1 0 0 1 1 0
1 1 1 1 1 1 1 1 0 0 1 0 1
1 1 1 1 1 1 1 1 0 0 0 0 1
1 1 1 1 1 1 1 1 0 0 0 1 X
1 1 1 1 1 1 1 1 1 1 0 X 0
1 0 0 0 1 i7 i6 i5 i4 i3 i2 i1 i0
1 ↓ – – – Ч
1
↓
– – –
Ч
1 ↓ – – – Ч
2
↓
– – –
Ч
2 ↓ – – – Ч
1
↑
– – –
Ч
1 ↑ – – – Ч
1
↓
– – –
Ч
1 ↓ – – – Ч
1
↓
– – –
Ч
1 ↓ – – – Ч
1
↓
– – – ●
1 ↓ – – – Ч
1
↓
– – –
Ч
1 ↓ – – – ●
2
↓
– – –
Ч
2
↓
– – –
Ч
2
↓
– – –
Ч
1
↓
– – –
Ч
1
↓
– –
Ч
1
↓
– –
Ч
1
↓
– –
Ч
1
↓
– – ●
1
↓
– –
Ч
1
↓
– – ●
1
↓
– –
Ч
1
↓
– –
Ч
1
↓
– –
Ч
1
↓
– –
Ч
1
↓
– – ●
1
↓
– –
Ч
1
↓
– – ●
1
↓
– –
Ч
1
↑ ↑ ↑ ↑ Ч
2
↓
– – ●
2
↓
– – ●
2
↓
– – ●
2
↓
– –
Ч
2
↓
– –
Ч
2
↓
– –
Ч
2
↓
– – ●
2 ↓ – – ●
2
↓
– – ●
2 ↓ – – Ч
2
↓
– –
Ч
2 ↓ – – Ч
1
↓
– – –
Ч
1 ↓ – – – Ч
1
Ч
1 ↓ – – – Ч
1
↓
– – –
Ч
1 ↓ – – – Ч
1
↓
– – –
Ч
1 ↓ – – – Ч
1
↓
– – –
Ч
1 ↓ – – – Ч
1
↓
– – –
Ч
3 ↓ – – – Ч
BA ← YH
BA
←
YL
BA ← imm8
A
←
[X], B
←
[X+1], X
←
X+2
A ← [Y], B ← [Y+1], Y ← Y+2
EXT
←
BA
EXT ← imm8
SP1
←
BA
SP2 ← BA
XH
←
BA
XL ← BA
XL
←
imm8
YH ← BA
YL
←
BA
YL ← imm8
[X]
←
A, [X+1]
←
B, X
←
X+2
[X]
←
i3~0, [X+1]
←
i7~4, X
←
X+2
[Y]
←
A, [Y+1]
←
B, Y
←
Y+2
No operation (PC
←
PC+1)
A
←
A
∨
A
A
←
A
∨
B
A
←
A
∨
imm4
A
←
A
∨
[X]
A
←
A
∨
[X], X
←
X+1
A
←
A
∨
[Y]
A
←
A
∨
[Y], Y
←
Y+1
B
←
B
∨
A
B
←
B
∨
B
B
←
B
∨
imm4
B
←
B
∨
[X]
B
←
B
∨
[X], X
←
X+1
B
←
B
∨
[Y]
B
←
B
∨
[Y], Y
←
Y+1
F
←
F
∨
imm4
[X]
←
[X]
∨
A
[X]
←
[X]
∨
B
[X]
←
[X]
∨
imm4
[X]
←
[X]
∨
A, X
←
X+1
[X]
←
[X]
∨
B, X
←
X+1
[X] ← [X]
∨
imm4, X ← X+1
[Y]
←
[Y]
∨
A
[Y] ← [Y]
∨
B
[Y]
←
[Y]
∨
imm4
[Y] ← [Y]
∨
A, Y ← Y+1
[Y]
←
[Y]
∨
B, Y
←
Y+1
[Y] ← [Y]
∨
imm4, Y ← Y+1
A
←
[SP2], SP2
←
SP2+1
B ← [SP2], SP2 ← SP2+1
F
←
[SP2], SP2
←
SP2+1
X ← ([SP1 ∗ 4+3]~[SP1 ∗ 4]), SP1 ← SP1+1
Y
←
([SP1
∗
4+3]~[SP1
∗
4]), SP1
←
SP1+1
[SP2-1] ← A, SP2 ← SP2-1
[SP2-1]
←
B, SP2
←
SP2-1
[SP2-1] ← F, SP2 ← SP2-1
([(SP1-1)
∗
4+3]~[(SP1-1)
∗
4])
←
X, SP1
←
SP1-1
([(SP1-1) ∗ 4+3]~[(SP1-1) ∗ 4]) ← Y, SP1 ← SP1-1
PC
←
([SP1
∗
4+3]~[SP1
∗
4]), SP1
←
SP1+1
PC
←
([SP1
∗
4+3]~[SP1
∗
4]), SP1
←
SP1+1
[X]
←
i3~0, [X+1]
←
i7~4, X
←
X+2
Mnemonic
Machine code
Operation Cycle Page
Flag EXT.
mode 12 E I C Z 11 10 9 8 7 6 5 4 3 2 1 0
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