Sample linker command file – Zilog EZ80F916 User Manual
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Using the ANSI C-Compiler
ZiLOG Developer Studio II
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User Manual
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Sample Linker Command File
The sample default linker command file for the standard link configuration is discussed
here as a good example of the contents of a linker command file in practice and how the
linker commands it contains work to configure your load file. The default linker command
file is automatically generated by the ZDS II IDE. If the project name is
test.zdspro
and your configuration is simply named
debug
, for example, the default linker command
file name is
test_debug.linkcmd
. You can add additional directives to the linking pro-
cess by specifying them in the Additional Linker Directives dialog box (see “Additional
Linker Directives Dialog Box” on page 82). Alternatively, you can define your own linker
command file by selecting the Use Existing button (see “Use Existing” on page 83).
__copy_code_to_ram
Flag indicating whether code is to be copied to RAM before executing
__stack
Top of stack is set as high address of available RAM
__heapbot
Base of heap for is set as low address of available RAM
__heaptop
Top of heap is set as high address of available RAM
__crtl
Flag indicating whether ZiLOG-supplied RTL is used
_<CSx>_LBR_INIT_PARAM
Chip select address lower bound initializer
_<CSx>_UBR_INIT_PARAM
Chip select address upper bound initializer
_<CSx>_CTL_INIT_PARAM
Chip select control initializer
_<CSx>_BMC_INIT_PARAM
Chip select bus mode initializer
__RAM_CTL_INIT_PARAM
On-chip RAM control initializer
__RAM_ADDR_U_INIT_PARAM
On-chip RAM address upper byte initializer
__FLASH_CTL_INIT_PARAM
On-chip Flash control initializer
__FLASH_ADDR_U_INIT_PARAM On-chip Flash address upper byte initializer
_SYS_CLK_FREQ
System clock frequency as selected in the Configure Target dialog box
_SYS_CLK_SRC
System clock source as selected in the Configure Target dialog box
_OSC_FREQ
Oscillator clock frequency (system clock)
_OSC_FREQ_MULT
On-chip phase-locked loop divider initializer
__PLL_CTL0_INIT_PARAM
On-chip phase-locked loop control register 0 initializer
_zsl_g_clock_xdefine
System clock frequency (this symbol used by ZSL)
Table 6. Linker Symbols (Continued)
Symbol Description