Zilog EZ80F916 - Manual (Page 118)

UM014423-0607 Using the Integrated Development Environment
ZiLOG Developer Studio II
eZ80Acclaim! ® User Manual
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9. Select the Enable Flash check box if you want to use internal Flash. Enter the address
in the Address Upper Byte (hex) field. This shifts Flash and affects the pages
displayed in the Flash Loader Processor dialog box. Select the number of wait states
from the Wait States drop-down list box. The wait states value is based on the value of
the system clock frequency according to the following table:
You can select any wait states value; however, 5, 6, and 7 are not recommended for
performance reasons. Based on the currently configured system clock frequency, ZDS
II suggests the appropriate wait states value by appending an asterisk to it in the Wait
States drop-down list box. The asterisk moves to different values when the system
clock frequency is changed in the same dialog box. When the target clock frequency is
changed, you must update the wait states value if needed.
10. To use the oscillator, select the Oscillator button and enter the frequency in the System
Clock Frequency (Hz) field.
11. To use the phase-locked loop, select the Phase-Locked Loop button, enter the clock
frequency in the System Clock Frequency (Hz) field, enter the oscillator frequency in
the Oscillator Frequency (Hz) field, select a charge pump current, and select a lock
criteria.
The eZ80F91 device contains a Phase-Locked Loop (PLL) module, the output of
which can be used as the system clock. This allows the application to run at 50 MHz
with an oscillator frequency between 1 and 10 MHz. Since the system defaults to
using the oscillator upon power-on or hardware reset, the application program must
enable and select the PLL as the source of the system clock. This also requires the ZDI
clock frequency to change if a debug session is started so that a reliable connection
can be maintained. ZDS automatically changes the rate after the first Reset or Go
command is invoked and the Change ZDI Clock Upon Reset check box has been
selected.
Wait States System Clock (MHz)
0 <12
1 12–23.9
2 24–35.9
3 36–47.9
4 48–59.9
5 60–71.9
6 72–84
7 >84