Address checking, Inter‑packet gap, Pause ignore – Altera 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 71: Inter-packet gap
Related Information
MAC Feature Configuration Registers
on page 3-105
Information about the
PAD_CONFIG
register.
Address Checking
The RX MAC supports all three types of addresses:
• Unicast—Specifies a destination address is a unicast (individual) address. Bit 0 is 0.
• Multicast—Specifies a destination address is a multicast or group address. Bit 0 is 1.
• Broadcast—Specifies a broadcast address when all 48 bits in the destination address are all 1s,
48’hFFFF_FFFF_FFFF.
If destination address matching is enabled, IP core address checking compares the address to the address
programmed in the destination address register, and accepts only the frames with a matching address.
You must enable filtering to discard mismatched destination addresses.
To enable address checking, you must turn ensure your 40-100GbE IP core has the following values in the
specified register fields:
• Bit 0 of the
RX_FILTER_CTRL
register at offset 0x103 has the value of 0.
• Bit 0 of the
MADDR_CTRL
register at offset 0x140 has the value of 1.
• Bit 30 of the
MADDR_CTRL
register has the value of 1.
The
MADDR_CTRL
fields allow you to turn off destination address checking but still enable the IP core to
filter RX traffic based on other criteria.
If bit 0 of the
RX_FILTER_CTRL
register has the value of 1, the IP core is in promiscuous receive mode. In
this mode, the IP core omits address checking and accepts all the Ethernet frames it receives, except
possibly runt frames.
Related Information
•
Information about the
MADDR_CTRL
register and related address-checking registers. Describes the
interactions between related register fields.
•
MAC Configuration and Filter Registers
Additional information about the filtering options, including information about the
RX_FILTER_CTRL
register.
Inter‑Packet Gap
The MAX RX removes all IPG octets received, and does not forward them to the client interface.
Pause Ignore
When the pause frame receive enable bits are not set, the IP core does not process incoming pause frames.
In this case, the MAC TX traffic is not affected by the valid pause frames.
You can enable unicast or multicast pause receive by setting the appropriate bits of the pause registers.
Related Information
•
Congestion and Flow Control Using Pause Frames
•
Pause Control and Generation Interface
on page 3-35
3-24
Address Checking
UG-01088
2014.12.15
Altera Corporation
Functional Description