Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 104)

Table 3-18: 40-100GbE MAC and PHY IP Core Without Adapters: Transmit Side Signals
Signal Name Direction Interface
mac_tx_arst_ST Input
Resets
pcs_tx_arst_ST Input
tx_serial [3:0]
(40GbE and
CAUI–4)
tx_serial [9:0]
(standard
100GbE)
Output Transceiver PHY serial data
interface
tx_lanes_stable Output PHY status
clk_txmac Input Clocks
TX client interface without
adapters (custom streaming
interface)
din[*64-1:0] Input
TX client interface without
adapters (custom streaming
interface)
din_start[-1:0] Input
din_end_pos[*8-1:0] Input
din_ack Output
pause_insert_tx Input
Pause control and generation
interface
The
_to_tx
signals are not
visible in duplex variations.
pause_insert_time[15:0] Input
pause_insert_mcast Input
pause_insert_dst[47:0] Input
pause_insert_src[47:0] Input
pause_match_to_tx Input
pause_time_to_tx[15:0] Input
remote_fault_to_tx Input Link fault signaling interface
These two signals are not visible
in duplex variations.
local_fault_to_tx Input
UG-01088
2014.12.15
Signals of MAC and PHY Variations Without Adapters 3-57
Functional Description Altera Corporation
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