Altera 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 196
June 2012
1.0
• Updated for use with version 12.0 of the Quartus II software.
• Updated address map.
• Updated device family support.
• Updated interfaces for 40-100GbE IP cores with adapters and without
adapters. Additional interfaces include:
• MAC and PHY asynchronous resets.
• MAC to PHY connections.
• Lane-to-lane deskew.
• Statistics counters increment vectors.
• Link fault signaling, including remote fault and local fault.
• Updated RTL hierarchy, directory structure, and wrapper reorganiza‐
tion.
• Feature additions:
• Controllable FCS (CRC) insertion and removal.
• Cut-through mode runt removal.
• PCS BER monitor.
• PCS test pattern generation and check.
• Reduced RX destination MAC address checking from 16 addresses to
1 address.
• Preserved FCS result.
• Statistics counters implemented as a synthesis option.
• Updated or added software registers:
• Test pattern counter.
• Link fault signaling.
• CRC configuration.
• MAC hardware error.
• MAC and PHY resets.
• PCS hardware error.
• BER monitor.
• Test mode.
• MAC address.
• Statistics counters: roll-overs and increment vectors.
• Clocking revisions:
•
clk50
has been removed and replaced by
clk_status
.
•
clk_din/clk_txmac
and
clk_dout/clk_rxmac
have been added as
TX and RX input clocks.
• Additional parameters:
STATS_CNTRS_OPTION
and
FAST_SIMULATION
.
• Updated testbenches and simulation examples.
• Updated reset signals and reset bits.
• Additional information regarding oversized frames.
UG-01088
2014.12.15
40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Revision
History
D-7
Additional Information
Altera Corporation