Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 132)

Address Name Bit Description HW Reset
Value
Access
0x010
IO_LOCKS
For the
CAUI-4 configu‐
ration only .
[31:26] Reserved. 0x3f R
[25:22] When asserted, indicates that the
corresponding TX PLL is locked.
0x0 R
[21:6] Reserved. 0xffff R
[5:2] When asserted, indicates that the
corresponding RX CDR is locked. The
lowest bit corresponds to lane 0 and so
forth.
1’b0 R
[1] When asserted, indicates that the TX
interface is ready.
1’b0 R
[0] When asserted, indicates that the RX
interface is ready.
1’b0 R
0x011
LOCKED_TIME
[31:0] Counts the RX continuous up time in
seconds. The counter will roll over in
approximately 126 years.
0x00000000 R
0x012
WORD_LOCKS
[19:0] When asserted, indicates that the
physical channel has identified 66 bit
block boundaries in the serial data
stream.
0x00000000 R
0x013
AM_LOCKS
[19:0] When asserted, indicates that the
physical channel has identified virtual
lane alignment markers in the data
stream.
0x00000000 R
UG-01088
2014.12.15
Lock Status Registers 3-85
Functional Description Altera Corporation
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