Altera 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
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Figure 1-1: 40GbE and 100GbE MAC and PHY MegaCore Function
Main block, internal connections, and external block requirements.
40- or 100-Gbps Ethernet MAC and PHY MegaCore Function
TX
FIFO
TX
MAC
RX
MAC
40- or 100-GbE MAC
PMA
PMA
PCS
PHY
TX
Adapter
PCS
XLGMII w/data_valid signal
or CGMII w/data_valid signal
4 x 40 bits or
10 x 40 bits
XLAUI: 4 x 10.3125 Gbps or
CAUI: 10 x 10.3125 Gbps
CAUI-4: 4 x 25.78125 Gbps
Custom Streaming
Avalon-ST
Avalon-ST
Control and
Status Interface
Avalon-MM
Avalon-MM
RX
Adapter
Custom Streaming
Reconfiguration
Controller
As illustrated, on the MAC client side you can choose a wide, standard Avalon
®
Streaming (Avalon-ST)
interface, or a narrower, custom streaming interface. Depending on the variant you choose, the MAC
client side Avalon Streaming (Avalon-ST) interface is either 256 or 512 bits of data mapped to either four
or ten 10.3125 Gbps transceiver PHY links, depending on data rate, or to four 25.78125 Gbps transceiver
PHY links.
The 40GbE (XLAUI) interface has 4x10.3125 Gbps links. The 100GbE (CAUI) interface has 10x10.3125
Gbps links. Several additional options are available. For Arria V GZ, Stratix IV, and Stratix V devices, you
can configure a lower-rate 40GbE option with 4x6.25 Gbps links. For Stratix V devices only, you can
configure a 40GbE 40GBASE-KR4 variation to support Backplane Ethernet. For Stratix V GT devices
only, you can configure a 100GbE CAUI-4 option, with 4x25.78125 Gbps links.
The FPGA serial transceivers are compliant with the IEEE 802.3ba standard XLAUI, CAUI, and CAUI-4
specifications. The IP core configures the transceivers to implement the relevant specification for your IP
core variation. You can connect the transceiver interfaces directly to an external physical medium
dependent (PMD) optical module or to another device.
You can configure and generate most configurations of the 40-100GbE IP core in transmit (TX) only,
receive (RX) only, or duplex mode. The 100GbE CAUI-4 option and the 40GBASE-KR4 options are
available in duplex mode only.
The IP core provides standard MAC and physical coding sublayer (PCS) functions with a variety of
configuration and status registers. You can exclude the statistics registers. If you exclude these registers,
you can monitor the statistics counter increment vectors that the IP core provides at the client side
interface and maintain your own counters.
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About the 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function
UG-01088
2014.12.15
Altera Corporation
About the 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function