Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 15)

Module ALMs Logic Registers
Memory
M9K
• • alt_e40_pcs_
tx:pcs_tx
3600 3900 0
• • alt_e40_phy_
csr:phy_csr
700 1100 0
• alt_e40_phy_pma_
siv:pma
600 500 0
Related Information
Fitter Resources Reports in the Quartus II Help
Information about Quartus II resource utilization reporting, including ALMs needed.
Resource Utilization for 100GbE IP Cores
Resource utilization changes if the statistics counters are configured in the IP core. You can specify
whether to include or not include the statistics counters in the 40-100GbE parameter editor, but you
cannot change the setting dynamically.
Table 1-6: 100GbE IP Core FPGA Resource Utilization in Stratix V and Arria V GZ Devices
Lists the resources and expected performance for selected variations of the 100GbE IP cores in an Arria V GZ or
Stratix V device. The results were obtained using the Quartus II software v13.1 for a Stratix V 5SGXEA7N2F45C2
device.
• Top-level modules are in bold.
• The numbers of ALMs and logic registers are rounded up to the nearest 100.
• The numbers of ALMs, before rounding, are the ALMs needed numbers from the Quartus II Fitter Report.
Module ALMs Logic Registers
Memory
M20K
MAC&PHY with
Avalon-ST client
interface without
statistics counters
45100 87700 28
MAC&PHY with
Avalon-ST client
interface and with
statistics counters
49700 95500 28
1-12 Resource Utilization for 100GbE IP Cores
UG-01088
2014.12.15
Altera Corporation About the 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function
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