Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 144)

Address Name Bit Description HW
Reset
Value
Access
0x0D1
Updated RX
Coef new,
Lane 1
[9]
When set to 1, indicates that new local device
coefficients are available for Lane 1. The LT logic
changes the local TX equalizer coefficients as
specified in 0xE1[23:16]. When set to 0,
continues normal operation. This bit self clears.
This override of normal operation can only
occur if 0xD0[17] (
Ovride Local RX Coef
enable
) has the value of 1. If 0xD0[17] has the
value of 0, this register field (0xD1[9]) has no
effect.
Register bit 0xD1[8] refers to Lane 0. This bit is
the equivalent of register 0xD1[8] for Lane 1.
(Refer to 10GBASE-KR PHY Register
Definitions ).
1'b0
RW
Updated RX
Coef new,
Lane 2
[10]
When set to 1, indicates that new local device
coefficients are available for Lane 2. The LT logic
changes the local TX equalizer coefficients as
specified in 0xE5[23:16]. When set to 0,
continues normal operation. This bit self clears.
This override of normal operation can only
occur if 0xD0[17] (
Ovride Local RX Coef
enable
) has the value of 1.
This bit is the equivalent of register 0xD1[9] for
Lane 2.
1'b0
RW
Updated RX
Coef new,
Lane 3
[11]
When set to 1, indicates that new local device
coefficients are available for lane 3. The LT logic
changes the local TX equalizer coefficients as
specified in 0xE9[23:16]. When set to 0,
continues normal operation. This bit self clears.
This override of normal operation can only
occur if 0xD0[17] (
Ovride Local RX Coef
enable
) has the value of 1.
This bit is the equivalent of register 0xD1[9] for
Lane 3.
1'b0
RW
UG-01088
2014.12.15
40GBASE-KR4 Registers 3-97
Functional Description Altera Corporation
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