Altera 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 13)

Module ALMs Logic Registers
Memory
M20K
40GBASE-KR4 PHY
• AN
• LT
• FEC
• Use M20K blocks
for FEC buffer
23800 24500 8
40GBASE-KR4 PHY
• AN
• LT
• FEC
• Do not use M20K
blocks for FEC
buffer
31900 41600 0
Table 1-5: 40GbE IP Core FPGA Resource Utilization in Stratix IV Devices
Lists the resources and expected performance for selected variations of the 40GbE IP cores in a Stratix IV device.
The results were obtained using the Quartus II software v13.1 for a Stratix IV EP4S100G5F45C2 device.
• Top-level modules are in bold.
• The numbers of ALMs and logic registers are rounded up to the nearest 100.
Module ALMs Logic Registers
Memory
M9K
MAC&PHY with
Avalon-ST client
interface without
statistics counters
18100 25000 20
MAC&PHY with
Avalon-ST client
interface and with
statistics counters
22100 32100 20
MAC with Avalon-ST
client interface
without statistics
counters
9700 15200 20
1-10 Resource Utilization for 40GbE IP Cores
UG-01088
2014.12.15
Altera Corporation About the 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function
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