Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Instruction Manuals and User Guides
We have 1 Instruction Manual and User Guide for 40-Gbps Ethernet MAC and PHY MegaCore Function Altera
Manuals 
| Recognized languages: | English |
|---|---|
| Pages: | 199 |
| Size: | 1.78 MB |
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Document Outline
- 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide
- Contents
- About the 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function
- Getting Started
- Installing and Licensing IP Cores
- Specifying the 40-100GbE IP Core Parameters and Options
- IP Core Parameters
- Files Generated for the 40-100GbE IP Core
- Simulating the IP Core
- Integrating Your IP Core in Your Design
- 40-100GbE IP Core Testbenches
- Simulating the 40‑100GbE IP Core With the Testbenches
- Compiling the Full Design and Programming the FPGA
- Initializing the IP Core
- Functional Description
- High Level System Overview
- 40-100GbE MAC and PHY Functional Description
- 40-100GbE IP Core TX Datapath
- 40-100GbE IP Core TX Data Bus Interfaces
- 40-100GbE IP Core RX Datapath
- 40-100GbE IP Core RX Data Bus Interfaces
- 40GbE Lower Rate 24.24 Gbps MAC and PHY
- 100GbE CAUI–4 PHY
- External Reconfiguration Controller
- Congestion and Flow Control Using Pause Frames
- Pause Control and Generation Interface
- Pause Control Frame and Non‑Pause Control Frame Filtering and Forwarding
- 40-100GbE IP Core Modes of Operation
- Link Fault Signaling Interface
- Statistics Counters Interface
- MAC – PHY XLGMII or CGMII Interface
- Lane to Lane Deskew Interface
- PCS Test Pattern Generation and Test Pattern Check
- Transceiver PHY Serial Data Interface
- 40GBASE-KR4 IP Core Variations
- Control and Status Interface
- Clocks
- Resets
- Signals
- Software Interface: Registers
- 40-100GbE IP Core Registers
- Transceiver PHY Control and Status Registers
- Lock Status Registers
- Bit Error Flag Registers
- PCS Hardware Error Register
- BER Monitor Register
- Test Mode Register
- Test Pattern Counter Register
- Link Fault Signaling Registers
- MAC and PHY Reset Registers
- PCS‑VLANE Registers
- PRBS Registers
- 40GBASE-KR4 Registers
- MAC Configuration and Filter Registers
- Pause Registers
- MAC Hardware Error Register
- CRC Configuration Register
- MAC Feature Configuration Registers
- MAC Address Registers
- Statistics Registers
- 40‑100GbE Example Design Registers
- 40-100GbE IP Core Registers
- Ethernet Glossary
- Debugging the 40GbE and 100GbE Link
- 40-100GbE IP Core Example Design
- Address Map Changes for the 40-100GbE IP Core v12.0 Release
- 10GBASE-KR Registers
- Additional Information