Altera Arria V Avalon-MM - Manual (Page 92)

Bit Name Access
Mode
Description
[2] INTC_RECEIVED_ENA RW When set to 1’b1, enables the assertion
of
CraIrq_o
when the Root Port
Interrupt Status register
INTC_
RECEIVED
bit indicates it has received
INTC.
[1] INTB_RECEIVED_ENA RW When set to 1’b1, enables the assertion
of
CraIrq_o
when the Root Port
Interrupt Status register
INTB_
RECEIVED
bit indicates it has received
INTB.
[0] INTA_RECEIVED_ENA RW When set to 1’b1, enables the assertion
of
CraIrq_o
when the Root Port
Interrupt Status register
INTA_
RECEIVED
bit indicates it has received
INTA.
Root Port TLP Data Registers
The TLP data registers provide a mechanism for the Application Layer to specify data that the Root Port
uses to construct Configuration TLPs, I/O TLPs, and single dword Memory Reads and Write requests.
The Root Port then drives the TLPs on the TLP Direct Channel to access the Configuration Space, I/O
space, or Endpoint memory.
5-30 Root Port TLP Data Registers
UG-01105_avmm
2014.12.15
Altera Corporation Registers
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