Altera Arria V Avalon-MM - Manual (Page 5)

Feature Avalon‑ST Interface Avalon‑MM Interface Avalon‑MM DMA
Out-of-order
completions
(transparent to the
Application Layer)
Not supported Supported Supported
Requests that cross 4
KByte address
boundary (transparent
to the Application
Layer)
Not supported Supported Supported
Polarity Inversion of
PIPE interface signals
Supported Supported Supported
ECRC forwarding on
RX and TX
Supported Not supported Not supported
Number of MSI
requests
1, 2, 4, 8, or 16 1, 2, 4, 8, or 16 1, 2, 4, 8, or 16
MSI-X Supported Supported Supported
Legacy interrupts Supported Supported Supported
Expansion ROM Supported Not supported Not supported
The purpose of the Arria VAvalon-MM Interface for PCIe Solutions User Guide is to explain how to use
this IP core and not to explain the PCI Express protocol. Although there is inevitable overlap between
these two purposes, this document should be used in conjunction with an understanding of the PCI
Express Base Specification.
Note: This release provides separate user guides for the different variants. The Related Information
provides links to all versions.
Related Information
• V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide
• Arria V Avalon-MM Interface for PCIe Solutions User Guide
• Arria V Avalon-ST Interface for PCIe Solutions User Guide
1-4 Features
UG-01105_avmm
2014.12.15
Altera Corporation Datasheet
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