Altera Arria V Avalon-MM - Manual (Page 22)

Base Address Register (BAR) Settings
You can configure up to six 32-bit BARs or three 64-bit BARs.
Table 3-2: BAR Registers
Parameter Value Description
Type
Disabled
64-bit prefetchable memory
32-bit non-prefetchable memory
32-bit prefetchable memory
I/O address space
Defining memory as prefetchable allows data in the
region to be fetched ahead anticipating that the
requestor may require more data from the same
region than was originally requested. If you specify
that a memory is prefetchable, it must have the
following 2 attributes:
• Reads do not have side effects
• Write merging is allowed
The 32-bit prefetchable memory and I/O address
space BARs are only available for the Legacy
Endpoint.
Size
Not configurable
Specifies the memory size calculated from other
parameters you enter.
Table 3-3: Device ID Registers
The following table lists the default values of the read-only Device ID registers. You can use the parameter editor
to change the values of these registers. Refer to Type 0 Configuration Space Registers for the layout of the Device
Identification registers.
Register Name Range Default Value Description
Vendor ID 16 bits 0x00000000 Sets the read-only value of the
Vendor ID
register. This
parameter cannot be set to 0xFFFF, per the PCI Express
Specification.
Address offset: 0x000.
Device ID 16 bits 0x00000001 Sets the read-only value of the
Device ID
register. This
register is only valid in the Type 0 (Endpoint) Configu‐
ration Space.
Address offset: 0x000.
UG-01105_avmm
2014.12.15
Base Address Register (BAR) Settings 3-3
Parameter Settings Altera Corporation
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