Altera Arria V Avalon-MM - Manual (Page 23)

Register Name Range Default Value Description
Revision ID 8 bits 0x00000001 Sets the read-only value of the
Revision ID
register.
Address offset: 0x008.
Class code 24 bits 0x00000000 Sets the read-only value of the
Class Code
register.
Address offset: 0x008.
Subsystem
Vendor ID
16 bits 0x00000000 Sets the read-only value of the
Subsystem Vendor ID
register in the PCI Type 0 Configuration Space. This
parameter cannot be set to 0xFFFF per the PCI Express
Base Specification. This value is assigned by PCI-SIG to
the device manufacturer. This register is only valid in
the Type 0 (Endpoint) Configuration Space.
Address offset: 0x02C.
Subsystem
Device ID
16 bits 0x00000000 Sets the read-only value of the
Subsystem Device ID
register in the PCI Type 0 Configuration Space.
Address offset: 0x02C
Related Information
PCI Express Base Specification 2.1 or 3.0
Device Capabilities
Table 3-4: Capabilities Registers
Parameter Possible Values Default Value Description
Maximum
payload size
128 bytes
256 bytes 128 bytes Specifies the maximum payload size supported. This
parameter sets the read-only value of the max payload
size supported field of the Device Capabilities register
(0x084[2:0]). Address: 0x084.
Completion
timeout
range
ABCD
BCD
ABC
AB
B
A
None
ABCD Indicates device function support for the optional
completion timeout programmability mechanism. This
mechanism allows system software to modify the
completion timeout value. This field is applicable only to
Root Ports and Endpoints that issue requests on their
own behalf. Completion timeouts are specified and
enabled in the Device Control 2 register (0x0A8) of the
PCI Express Capability Structure Version. For all other
3-4 Device Capabilities
UG-01105_avmm
2014.12.15
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