Altera Arria V Avalon-MM - Manual (Page 78)

Bit Name Access Description
[15:0]
AVL_IRQ_ASSERTED[15:0]
RO Current value of the Avalon-MM interrupt
(IRQ) input ports to the Avalon-MM RX
master port:
• 0—Avalon-MM IRQ is not being
signaled.
• 1—Avalon-MM IRQ is being signaled.
A Qsys-generated IP Compiler for PCI
Express has as many as 16 distinct IRQ
input ports. Each
AVL_IRQ_ASSERTED[]
bit
reflects the value on the corresponding IRQ
input port.
Avalon-MM to PCI Express Interrupt Enable Registers
A PCI Express interrupt can be asserted for any of the conditions registered in the
Avalon-MM to PCI
Express Interrupt Status
register by setting the corresponding bits in the Avalon-MM-to-PCI Express
Interrupt Enable
register. Either MSI or legacy interrupts can be generated as explained in the section
Enabling MSI or Legacy Interrupts
Table 5-14: Avalon-MM to PCI Express Interrupt Enable Register, 0x0050
Bits Name Access Description
[31:24] Reserved N/A N/A
[23:16] A2P_MB_IRQ RW Enables generation of PCI Express
interrupts when a specified mailbox is
written to by an external Avalon-MM
master.
[4:0] AVL_IRQ[15:0] RW Enables generation of PCI Express
interrupts when a specified Avalon-MM
interrupt signal is asserted. Your Qsys
system may have as many as 16
individual input interrupt signals.
Table 5-15: Avalon-MM Interrupt Vector Register - 0x0060
Bits Name Access Description
[31:5] Reserved N/A N/A
5-16 Avalon-MM to PCI Express Interrupt Enable Registers
UG-01105_avmm
2014.12.15
Altera Corporation Registers
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