Altera Arria V Avalon-MM - Manual (Page 18)

Files Generated for Altera IP Cores
Figure 2-3: IP Core Generated Files
The Quartus II software generates the following output for your IP core.
Notes:
1. If supported and enabled for your IP variation
2. If functional simulation models are generated
_bb.v - Verilog HDL black box EDA synthesis file
_inst.v or .vhd - Sample instantiation template
synthesis - IP synthesis files
.qip - Lists files for synthesis
testbench - Simulation testbench files
1
- Testbench for supported simulators
.v or .vhd - Top-level IP variation synthesis file
simulation - IP simulation files
.sip - NativeLink simulation integration file
- Simulator setup scripts
- IP core variation files
.qip or .qsys - System or IP integration file
_generation.rpt - IP generation report
.bsf - Block symbol schematic file
.ppf - XML I/O pin information file
.spd - Combines individual simulation startup scripts
1
.html - Contains memory map
.sopcinfo - Software tool-chain integration file
_syn.v or .vhd - Timing & resource estimation netlist 1
.debuginfo - Lists files for synthesis
.v, .vhd, .vo, .vho - HDL or IPFS models
2
_tb - Testbench for supported simulators
_tb.v or .vhd - Top-level HDL testbench file
Programming a Device
After you compile your design, you can program your targeted Altera device and verify your design in
hardware.
For more information about programming Altera FPGAs, refer to Quartus II Programmer.
UG-01105_avmm
2014.12.15
Programming a Device 2-7
Getting Started with the Avalon‑MM Arria V Hard IP for PCI Express Altera Corporation
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