Altera Arria V Avalon-MM - Manual (Page 56)

Related Information
Pin-out Files for Altera Devices
Physical Layout of Hard IP in Arria V Devices
/>Arria V devices include one or two Hard IP for PCI Express IP cores. The following figures illustrate the
placement of the PCIe IP cores, transceiver banks, and channels. Note that the bottom left IP core
includes the CvP functionality. The other Hard IP blocks do not include the CvP functionality.
Transceiver channels are arranged in groups of six. For GX devices, the lowest six channels on the left side
of the device are labeled GXB_L0, the next group is GXB_L1, and so on. Channels on the right side of the
device are labeled GXB_R0, GXB_R1, and so on. Be sure to connect the Hard IP for PCI Express on the
left side of the device to appropriate channels on the left side of the device, as specified in the Pin-out Files
for Altera Devices.
Figure 4-8: Arria V Transceiver Bank and Hard IP for PCI Express IP Core Locations in Arria V GX and GT
Devices
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
9 Ch 18 Ch
36 Ch
24 Ch
GXB_L2
GXB_L1
GXB_L0
GXB_R2
GXB_R1
GXB_R0
PCIe
Hard IP
with
CvP
PCIe
Hard
IP
Notes:
1. Green blocks are 10-Gbps channels.
2. Blue blocks are 6-Gbps channels.
4-26 Physical Layout of Hard IP in Arria V Devices
UG-01105_avmm
2014.12.15
Altera Corporation Interfaces and Signal Descriptions
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