Altera Arria V Avalon-MM - Manual (Page 118)

Figure 9-1: Arria V Hard IP for PCI Express Using the Avalon-MM Interface
Clock
Domain
Crossing
(CDC)
Data
Link
Layer
(DLL)
Transaction
Layer (TL)
PHYMAC
Hard IP for PCI Express
Avalon-MM
TX Master
Avalon-MM
TX Slave
Avalon-MM
CRA Slave
(optional)
Reconfiguration
PIPE
Application
Layer
Clock & Reset
Selection
Configuration
Block
Configuration
Space
PCS PMA
Physical Layer
(Transceivers)
Configuration via PCIe Link
RX Buffer
PHY IP Core for
PCI Express (PIPE)
Avalon-MM
Bridge
Table 9-1: Application Layer Clock Frequencies
Lanes Gen1 Gen2
×1 125 MHz @ 64 bits or
62.5 MHz @ 64 bits
125 MHz @ 64 bits
×2 125 MHz @ 64 bits 125 MHz @ 64 bits
×4 125 MHz @ 64 bits 125 MHz @ 128 bits
×8 125 MHz @ 128 bits
N/A
Related Information
PCI Express Base Specification 2.1 or 3.0
Top-Level Interfaces
Avalon-MM Interface
An Avalon-MM interface connects the Application Layer and the Transaction Layer. The Avalon-MM
interface implement the Avalon-MM protocol described in the Avalon Interface Specifications. Refer to
this specification for information about the Avalon-MM protocol, including timing diagrams.
9-2 Top-Level Interfaces
UG-01105_avmm
2014.12.15
Altera Corporation IP Core Architecture
Send Feedback