Altera Arria V Avalon-MM User Manual
Page 132
Figure 9-6: Qsys System for PCI Express with Poor Address Space Utilization
The following figure uses a filter to hide the Conduit interfaces that are not relevant in this discussion.
Figure 9-7: Poor Address Map
The following figure illustrates the address map for this system.
The auto-assigned base addresses result in the following three large BARs:
• BAR0 is 28 bits. This is the optimal size because it addresses the Offchip_Data_Mem which requires
28 address bits.
• BAR2 is 29 bits. BAR2 addresses the Quick_Data_Mem which is 4 KBytes;. It should only require 12
address bits; however, it is consuming 512 MBytes of address space.
• BAR4 is also 29 bits. BAR4 address PCIe Cra is 16 KBytes. It should only require 14 address bits;
however, it is also consuming 512 MBytes of address space.
9-16
Minimizing BAR Sizes and the PCIe Address Space
UG-01105_avmm
2014.12.15
Altera Corporation
IP Core Architecture