Altera Arria V Avalon-MM - Manual (Page 82)

Bits Name Access Description
1 ERR_PCI_READ_FAILURE RW1C When set to 1, indicates the failure of a
PCI Express read. This bit can also be
cleared by writing a 1 to the same bit in
the
Avalon MM to PCI Express
Interrupt Status
register.
[15:2] Reserved — —
[16] P2A_MAILBOX_INT0 RW1C 1 when the P2A_MAILBOX0 is written
[17] P2A_MAILBOX_INT1 RW1C 1 when the P2A_MAILBOX1 is written
[18] P2A_MAILBOX_INT2 RW1C 1 when the P2A_MAILBOX2 is written
[19] P2A_MAILBOX_INT3 RW1C 1 when the P2A_MAILBOX3 is written
[20] P2A_MAILBOX_INT4 RW1C 1 when the P2A_MAILBOX4 is written
[21] P2A_MAILBOX_INT5 RW1C 1 when the P2A_MAILBOX5 is written
[22] P2A_MAILBOX_INT6 RW1C 1 when the P2A_MAILBOX6 is written
[23] P2A_MAILBOX_INT7 RW1C 1 when the P2A_MAILBOX7 is written
[31:24] Reserved — —
An Avalon-MM interrupt can be asserted for any of the conditions noted in the
Avalon-MM Interrupt
Status
register by setting the corresponding bits in the
PCI Express to Avalon-MM Interrupt Enable
register.
PCI Express interrupts can also be enabled for all of the error conditions described. However, it is likely
that only one of the Avalon-MM or PCI Express interrupts can be enabled for any given bit. Typically, a
single process in either the PCI Express or Avalon-MM domain handles the condition reported by the
interrupt.
5-20 PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
UG-01105_avmm
2014.12.15
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