Altera Arria V Avalon-MM - Manual (Page 88)

Byte Offset
Register Dir Description
• 10011: Loopback.Exit
• 10100: Hot.Reset
• 10101: LOs
• 11001: L2.transmit.Wake
• 11010: Speed.Recovery
• 11011: Recovery.Equalization, Phase 0
• 11100: Recovery.Equalization, Phase 1
• 11101: Recovery.Equalization, Phase 2
• 11110: recovery.Equalization, Phase 3
14'h3C68
current_speed_reg[1:0] O Indicates the current speed of the PCIe link. The
following encodings are defined:
• 2b’00: Undefined
• 2b’01: Gen1
• 2b’10: Gen2
• 2b’11: Gen3
14'h3C6C
lane_act_reg[3:0] O Lane Active Mode: This signal indicates the number
of lanes that configured during link training. The
following encodings are defined:
• 4’b0001: 1 lane
• 4’b0010: 2 lanes
• 4’b0100: 4 lanes
• 4’b1000: 8 lanes
Programming Model for Avalon‑MM Root Port
The Application Layer writes the Root Port TLP TX Data registers with TLP formatted data for Configu‐
ration Read and Write Requests, Message TLPs, I/O Read and Write Requests, or single dword Memory
Read and Write Requests. Software should check the Root Port
Link Status
register (offset 0x92) to
ensure the Data Link Layer Link
Active
bit is set to 1'b1 before issuing a Configuration request to
downstream ports.
The Application Layer data must be in the appropriate TLP format with the data payload aligned to the
TLP address. Aligning the payload data to the TLP address may result in the payload data being either
aligned or unaligned to the qword. The following figure illustrates three dword TLPs with data that is
aligned and unaligned to the qword.
5-26 Programming Model for Avalon‑MM Root Port
UG-01105_avmm
2014.12.15
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