Altera Arria V Avalon-MM - Manual (Page 115)

Poisoned TLPs can also set the parity error bits in the PCI Configuration Space Status register.
Table 8-5: Parity Error Conditions
Status Bit Conditions
Detected parity error (status register bit 15) Set when any received TLP is poisoned.
Master data parity error (status register bit 8) This bit is set when the command register parity
enable bit is set and one of the following conditions
is true:
• The poisoned bit is set during the transmission
of a Write Request TLP.
• The poisoned bit is set on a received completion
TLP.
Poisoned packets received by the Hard IP block are passed to the Application Layer. Poisoned transmit
TLPs are similarly sent to the link.
Related Information
PCI Express Base Specification 2.1 and 3.0
Uncorrectable and Correctable Error Status Bits
The following section is reprinted with the permission of PCI-SIG. Copyright 2010 PCI-SIG.
Figure 8-1: Uncorrectable Error Status Register
The default value of all the bits of this register is 0. An error status bit that is set indicates that the error
condition it represents has been detected. Software may clear the error status by writing a 1 to the
appropriate bit.
Rsvd Rsvd Rsvd
TLP Prefix Blocked Error Status
AtomicOp Egress Blocked Status
MC Blocked TLP Status
Uncorrectable Internal Error Status
ACS Violation Status
Unsupported Request Error Status
ECRC Error Status
Malformed TLP Status
Receiver Overflow Status
Unexpected Completion Status
Completer Abort Status
Completion Timeout Status
Flow Control Protocol Status
Poisoned TLP Status
Surprise Down Error Status
Data Link Protocol Error Status
Undefined
22 21 20 19 26 25 24 23 18 17 16 15 14 13 12 11 6 5 4 3 1 0 31
UG-01105_avmm
2014.12.15
Uncorrectable and Correctable Error Status Bits 8-7
Error Handling Altera Corporation
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