Altera Arria V Avalon-MM - Manual (Page 15)

The driver performs the following transactions with status of the transactions displayed in the ModelSim
simulation message window:
1. Various configuration accesses to the Avalon-MM Arria V Hard IP for PCI Express in your system
after the link is initialized
2. Setup of the Address Translation Table for requests that are coming from the DMA component
3. Setup of the DMA controller to read 512 Bytes of data from the Transaction Layer Direct BFM shared
memory
4. Setup of the DMA controller to write the same data back to the Transaction Layer Direct BFM shared
memory
5. Data comparison and report of any mismatch
Related Information
Simulating Altera Designs
Running A Gate-Level Simulation
The PCI Express testbenches run simulations at the register transfer level (RTL). However, it is possible to
create you own gate-level simulations. Contact your Altera Sales Representative for instructions and an
example that illustrate how to create a gate-level simulation from the RTL testbench.
Simulating the Single DWord Design
You can use the same testbench to simulate the Completer-Only Single Dword IP core by changing the
settings in the driver file.
1. In a terminal window, change to the
//testbench/_tb/simulation/submodules
directory.
2. Open altpcietb_bfm_driver_avmm.v in your text editor.
3. To enable target memory tests and specify the completer-only single dword variant, specify the
following parameters:
a.
parameter RUN_TGT_MEM_TST = 1;
b.
parameter RUN_DMA_MEM_TST = 0;
c.
parameter AVALON_MM_LITE = 1;
4. Change to the
/variant/testbench/mentor directory.
5. Start the ModelSim simulator.
6. To run the simulation, type the following commands in a terminal window:
a.
do msim_setup.tcl
b.
ld_debug
(The debug suffix stops optimizations, improving visibility in the ModelSim waveforms.)
c.
run 140000 ns
2-4 Running A Gate-Level Simulation
UG-01105_avmm
2014.12.15
Altera Corporation Getting Started with the Avalon‑MM Arria V Hard IP for PCI Express
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